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BU9844GUL-W Datasheet(PDF) 3 Page - Rohm |
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BU9844GUL-W Datasheet(HTML) 3 Page - Rohm |
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3 / 30 page  Datasheet Datasheet 3/26 TSZ02201-0R2R0G100470-1-2 © 2012 ROHM Co., Ltd. All rights reserved. 17.Sep.2013 Rev.002 www.rohm.com TSZ22111・15・001 BU9844GUL-W (16Kbit) Action timing characteristics (Unless otherwise specified, Ta=-40°C to +85°C, VCC =1.7V to 5.5V) Parameter Symbol FAST-MODE 2.5V ≤VCC≤5.5V STANDARD-MODE 1.7V ≤VCC≤5.5V Unit Min. Typ. Max. Min. Typ. Max. SCL Frequency fSCL - - 400 - - 100 kHz Data Clock “HIGH” Time tHIGH 0.6 - - 4.0 - - μs Data Clock “LOW” Time tLOW 1.2 - - 4.7 - - μs SDA, SCL Rise Time (Note1) tR - - 0.3 - - 1.0 μs SDA< SCL Fall Time (Note1) tF - - 0.3 - - 0.3 μs Start Condition Hold Time tHD:STA 0.6 - - 4.0 - - μs Start Condition Setup Time tSU:STA 0.6 - - 4.7 - - μs Input Data Hold Time tHD:DAT 0 - - 0 - - ns Input Data Setup Time tSU:DAT 100 - - 250 - - ns Output Data Delay Time tPD 0.1 - 0.9 0.2 - 3.5 μs Output Data Hold Time tDH 0.1 - - 0.2 - - μs Stop Condition Setup Time tSU:STO 0.6 - - 4.7 - - μs Bus Release Time Before Transfer Start tBUF 1.2 - - 4.7 - - μs Internal Write Cycle Time tWR - - 5 - - 5 ms Noise Removal Valid Period (SDA, SCL terminal) tI - - 0.1 - - 0.1 μs WP Hold Time tHD:WP 0 - - 0 - - ns WP Setup Time tSU:WP 0.1 - - 0.1 - - μs WP Valid Time tHIGH:WP 1.0 - - 1.0 - - μs (Note1) Not 100% tested. Sync Data Input / Output Timing SCL SDA WP ｔHD：WP stop condition ｔWR D1 D0 ACK ACK DATA(1) DATA(n) tSU ：WP ○Input read at the rise edge of SCL ○Data output in sync with the fall of SCL Figure 1-(a) Sync data input / output timing Figure 1-(b) Start – stop bit timing Figure 1-(d) WP timing at write execution Figure 1-(e) WP timing at write cancel ○At write execution, in the area from the DO taken clock rise of the first DATA (1), to tWR, set WP=”LOW” ○By setting WP “HIGH” in the area, write can be cancelled. When it is set WP=”HIGH” during tWR, write is forcibly ended, and data of address under access is not guaranteed, therefore write it once again. Figure 1-(c) Write cycle timing SDA (Input) SCL SDA (Output) tHD:STA tHD:DAT tSU:DAT tBUF tPD tDH tLOW tHIGH tR tF SDA D0 ACK tWR SCL Write data (n-th address) Stop condition Start condition tHIGH:WP WP SDA D1 D0 ACK ACK DATA(1) DATA(n) tWR SCL SDA tSU:STA tSU:STO tHD:STA START BIT STOP BIT SCL |
Similar Part No. - BU9844GUL-W_13 |
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Similar Description - BU9844GUL-W_13 |
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