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BR25S32F-WTR Datasheet(PDF) 3 Page - Rohm |
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BR25S32F-WTR Datasheet(HTML) 3 Page - Rohm |
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3 / 35 page  Datasheet 3/31 BR25Sxxx-W Series (32K 64K 128K 256K) TSZ02201-0R2R0G100330-1-2 21.AUG.2012 Rev.001 ©2012 ROHM Co., Ltd. All rights reserved. TSZ22111･15･001 www.rohm.com ●Operating timing characteristics (Ta=-40°C to +85°C, unless otherwise specified, load capacity CL=30pF) 1.7≦Vcc<2.5V 1.8≦Vcc<2.5V 2.5≦Vcc<4.5V 4.5≦Vcc<5.5V Parameter Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit SCK frequency fSCK - - 3 - - 5 - - 10 - - 20 MHz SCK high time tSCKWH 125 - - 80 - - 40 - - 20 - - ns SCK low time tSCKWL 125 - - 80 - - 40 - - 20 - - ns CSB high time tCS 250 - - 90 - - 40 - - 20 - - ns CSB setup time tCSS 100 - - 60 - - 30 - - 15 - - ns CSB hold time tCSH 100 - - 60 - - 30 - - 15 - - ns SCK setup time tSCKS 100 - - 50 - - 20 - - 15 - - ns SCK hold time tSCKH 100 - - 50 - - 20 - - 15 - - ns SI setup time tDIS 30 - - 20 - - 10 - - 5 - - ns SI hold time tDIH 50 - - 20 - - 10 - - 5 - - ns Data output delay time tPD - - 125 - - 80 - - 40 - - 20 ns Output hold time tOH 0 - - 0 - - 0 - - 0 - - ns Output disable time tOZ - - 200 - - 80 - - 40 - - 20 ns HOLDB setting setup time tHFS 100 - - 0 - - 0 - - 0 - - ns HOLDB setting hold time tHFH 100 - - 20 - - 10 - - 5 - - ns HOLDB release setup time tHRS 100 - - 0 - - 0 - - 0 - - ns HOLDB release hold time tHRH 100 - - 20 - - 10 - - 5 - - ns Time from HOLDB to output High-Z tHOZ - - 100 - - 80 - - 40 - - 20 ns Time from HOLDB to output change tHPD - - 100 - - 80 - - 40 - - 20 ns SCK rise time *1 tRC - - 1 - - 1 - - 1 - - 1 μs SCK fall time *1 tFC - - 1 - - 1 - - 1 - - 1 μs OUTPUT rise time *1 tRO - - 100 - - 50 - - 40 - - 20 ns OUTPUT fall time *1 tFO - - 100 - - 50 - - 40 - - 20 ns Write time tE/W - - 5 - - 5 - - 5 - - 5 ms *1 NOT 100% TESTED ●AC timing characteristics conditions Limits Parameter Symbol Min. Typ. Max. Unit Load capacity CL - - 30 pF Input rise time - - - 50 ns Input fall time - - - 50 ns Input voltage - 0.2Vcc/0.8Vcc V Input / Output judgment voltage - 0.3Vcc/0.7Vcc V ●Sync data input / output timing Figure 1. Input timing CSB SCK SI SO tCS tCSS tSCKS tSCKWL tSCKWH tDIS tDIH tRC tFC High-Z SI is taken into IC inside in sync with data rise edge of SCK. Input address and data from the most significant bit MSB Figure 2. Input / Output timing CSB SCK SI SO tPD tOH tRO,tFO tOZ tCSH tSCKH tCS High-Z Figure 3. HOLD timing CSB SCK SI n+1 "H" "L" n Dn n-1 Dn Dn-1 HOLDB SO Dn+1 tHFS tHFH tHOZ tHRS tHRH tDIS tHPD High-Z SO is output in sync with data fall edge of SCK. Data is output from the most significant bit MSB. |
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