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APPLICATION INFORMATION

GENERAL FUNCTION

REF

CODE

0x1000

[V]

(1)

SERIAL INTERFACE

SCLK

FS

DIN

SCLK

FS

F15

F15

X

X

E0

X

E1

E14

E15

D0

D1

D14

D15

X

DIN

F15

F15

X

X

E1

E0

E14

E15

X

D0

D1

D14

D15

X

DSP Mode:

µC Mode:

TLV5608

TLV5610

TLV5629

SLAS268E – MAY 2000 – REVISED MARCH 2004

The TLV5610, TLV5608, and TLV5629 are 8-channel, 12-bit, single-supply DACs, based on a resistor string

architecture. They consist of a serial interface, a speed and power-down control logic, a reference input buffer, a

resistor string, and a rail-to-rail output buffer.

The output voltage (full scale determined by external reference) for each channel is given by:

where REF is the reference voltage and CODE is the digital input value. The input range is 0x000 to 0xFFF for

the TLV5610, 0x000 to 0xFFC for the TLV5608, and 0x000 to 0xFF0 for the TLV5629. A power-on-reset initially

puts the internal latches to a defined state (all bits zero).

A falling edge of FS starts shifting the data on DIN starting with the MSB to the internal register on the falling

edges of SCLK. After 16 bits have been transferred, the content of the shift register is moved to one of the DAC

holding registers, depending on the address bits within the data word. A logic 0 on the LDAC pin is required to

transfer the content of the DAC holding register to the DAC latch and to update the DAC outputs. LDAC is an

asynchronous input. It can be held low if a simultaneous update of all eight channels is not needed.

For daisy-chaining, DOUT provides the data sampled on DIN with a delay of 16 clock cycles.

Figure 13. Data Sampled on DIN

Difference between DSP mode (MODE = N.C. or 0) and µC (MODE = 1) mode:

•

In µC mode, FS needs to be held low until all 16 data bits have been transferred. If FS is driven high before

the 16th falling clock edge, the data transfer is cancelled. The DAC is updated after a rising edge on FS.

•

In DSP mode, FS needs to stay low for 20 ns and can go high before the 16th falling clock edge.

•

In DSP mode there needs to be one falling SCLK edge before FS goes low to start the write (DIN) cycle.

•

In µC mode, the extra falling SCLK edge is not necessary. However, if it does happen, the extra negative

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