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VP101-3BADP Datasheet(PDF) 7 Page - Zarlink Semiconductor Inc

Part # VP101-3BADP
Description  30/50MHz 8-BIT CMOS VIDEO DAC
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

VP101-3BADP Datasheet(HTML) 7 Page - Zarlink Semiconductor Inc

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VP101
6
APPLICATION NOTES
RS-343A and RS-170 Video Generation
For generation of RS-343A compatible video levels it is
recommended that a doubly terminated 75
Ω load be used
with an RSET resistor value of approximately 542Ω
Similarly for generation of RS-170-compatible video, it is
recommended that a singly terminated 75
Ω load be used
with an RSET value of about 774Ω. If the VP101 is not driving
a large capacitive load, there will be negligible difference in
video quality between doubly terminated 75
Ω and singly
terminated 75
Ω loads.t
If driving a large capacitive load (load RC >1/20IIfc) it is
recommended that an output buffer with unloaded gain >2 be
used to drive a doubly terminated 75
Ω load.
COMP Resistor
To optimise the settling time of the VP101, a resistor
may be added in series between the COMP capacitor and
COMP pin. The series resistor damps inductive ringing on
COMP, thus improving settling time.
Non-Video Applications
The VP101 may be used in non-video applications by
disabling the video specific control inputs. REF WHITE
should be a logic ‘0’ while BLANC and SYNC should be a
logic ‘1’. ISYNC should be connected to VAA or AGND. All
three outputs will have the same full scale output current.
The relationship between RSET and full scale output
current (IOUT) in this configuration is as follows:
Iout (mA) = 7968 X −−−−−−− ≡ 255 LSBs
Note that 1 LSB
With the data inputs at $00, there is a DC offset current (Imin)
defined as follows:
Imin (mA) = 656 X −−−−−−− ≡ 21 LSBs
Therefore the total full scale output current will be IOUT +
Imin. The REF WHITE input may optionally be used as a
‘force to full scale’ control.
Fig.4 Input/output timing
VREF (V)
RSET (Ω)
VREF (V)
RSET (Ω)
VREF (V)
32 X RSET (Ω)
TIMING WAVEFORMS
NOTES
1. Output delay, tDLY, measured from the 50% point of the rising edge of CLOCK to the 50% point of full scale transition.
2. Settling time, ts, measured from the 50% point of full scale transition to the output remaining within ± 1 LSB.
3. Output rise/fall time, tVRF, measured between the 10% and 90% points of full scale transition.


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