 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
VPC3200A Datasheet(PDF) 8 Page - Micronas |
|
||||||||||||||||||||||||||||||
VPC3200A Datasheet(HTML) 8 Page - Micronas |
|
|
8 / 78 page  VPC 323xD, VPC 324xD ADVANCE INFORMATION 8 Micronas 2. Functional Description 2.1. Analog Video Front-End This block provides the analog interfaces to all video inputs and mainly carries out analog-to-digital conver- sion for the following digital video processing. A block diagram is given in Fig. 2–1. Most of the functional blocks in the front-end are digi- tally controlled (clamping, AGC, and clock-DCO). The control loops are closed by the Fast Processor (‘FP’) embedded in the decoder. 2.1.1. Input Selector Up to five analog inputs can be connected. Four inputs are for composite video or S-VHS luma signal. These inputs are clamped to the sync back porch and are ampli- fied by a variable gain amplifier. One input is for connec- tion of S-VHS carrier-chrominance signal. This input is internally biased and has a fixed gain amplifier. A second S-VHS chroma signal can be connected video-input VIN1. 2.1.2. Clamping The composite video input signals are AC coupled to the IC. The clamping voltage is stored on the coupling capacitors and is generated by digitally controlled cur- rent sources. The clamping level is the back porch of the video signal. S-VHS chroma is also AC coupled. The input pin is internally biased to the center of the ADC input range. 2.1.3. Automatic Gain Control A digitally working automatic gain control adjusts the magnitude of the selected baseband by +6/–4.5 dB in 64 logarithmic steps to the optimal range of the ADC. The gain of the video input stage including the ADC is 213 steps/V with the AGC set to 0 dB. 2.1.4. Analog-to-Digital Converters Two ADCs are provided to digitize the input signals. Each converter runs with 20.25 MHz and has 8 bit res- olution. An integrated bandgap circuit generates the required reference voltages for the converters. The two ADCs are of a 2-stage subranging type. 2.1.5. Digitally Controlled Clock Oscillator The clock generation is also a part of the analog front end. The crystal oscillator is controlled digitally by the control processor; the clock frequency can be adjusted within ±150 ppm. 2.1.6. Analog Video Output The input signal of the Luma ADC is available at the analog video output pin. The signal at this pin must be buffered by a source follower. The output voltage is 2 V, thus the signal can be used to drive a 75 Ω line. The magnitude is adjusted with an AGC in 8 steps together with the main AGC. Fig. 2–1: Analog front-end VIN3 VIN2 VIN1 CIN VIN4 bias ADC ADC gain clamp frequency reference generation DVCO ±150 ppm AGC +6/–4.5 dB digital CVBS or Luma digital Chroma system clocks 20.25 MHz Analog Video Output CVBS/Y CVBS/Y CVBS/Y CVBS/Y/C C |
Similar Part No. - VPC3200A |
|
Similar Description - VPC3200A |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
