ADS8324

9

SBAS172A

www.ti.com

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

Analog Input Sample Time

4.5

5.0

Clk Cycles

Conversion Time

16

Clk Cycles

Throughput Rate

50

kHz

CS Falling to

0

ns

DCLOCK LOW

CS Falling to

50

ns

DCLOCK Rising

DCLOCK Falling to

5

20

ns

DCLOCK Falling to Next

100

250

ns

50

100

ns

100

200

ns

Enabled

50

150

ns

75

200

ns

FIGURE 5. ADS8324 Basic Timing Diagrams.

DIGITAL INTERFACE

SIGNAL LEVELS

CMOS logic input, then that IC may require more supply

current than normal and may have a slightly longer propaga-

tion delay.

SERIAL INTERFACE

The ADS8324 communicates with microprocessors and

other digital systems via a synchronous 3-wire serial inter-

face, as shown in Figure 5 and Table I. The DCLOCK signal

synchronizes the data transfer with each bit being transmit-

ted on the falling edge of DCLOCK. Most receiving systems

will capture the bitstream on the rising edge of DCLOCK.

the system can use the falling edge of DCLOCK to

capture each bit.

A falling CS signal initiates the conversion and data transfer.

The first 4.5 to 5.0 clock periods of the conversion cycle are

used to sample the input signal. After the fifth falling

value for one clock period. For the next 16 DCLOCK

nificant bit first followed by two zeros on clock cycles 15

and 16. After the two zero “dummy bits” have been output,

subsequent clocks will repeat the output data but in a least

significant bit first format starting with a zero.

CS must be taken HIGH following a conversion in order to

place DOUT in tri-state. Subsequent clocks will have no

effect on the converter. A new conversion is initiated only

when CS has been taken HIGH and returned LOW.

DATA FORMAT

The output data from the ADS8324 is in Binary Two’s

Complement format, as shown in Table II. This table repre-

sents the ideal output code for the given input voltage and

does not include the effects of offset, gain error, or noise.

+85

°C.

See Figure 6 for test conditions.

CS/SHDN

D

OUT

DCLOCK

Complete Cycle

Power Down

Conversion

Sample

Use positive clock edge for data transfer

t

SUCS

t

CONV

t

SMPL

NOTE: Minimum 22 clock cycles required for 14-bit conversion. Shown are 24 clock cycles.

If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again.

B13

(MSB)

B12 B11 B10 B9

B8

B7

B6

B0

(LSB)

00

B5

B4

B3

B1

B2

Hi-Z

0

Hi-Z

t

CSD

DESCRIPTION

ANALOG VALUE

Full-Scale Range

Least Significant

Bit (LSB)

BINARY CODE

HEX CODE

+Full Scale

0111 1111 1111 1100

7FFC

Midscale

0V

0000 0000 0000 0000

0000

Midscale – 1LSB

0V – 1 LSB

1111 1111 1111 1100

FFFC

–Full Scale

1000 0000 0000 0000

8000

DIGITAL OUTPUT

BINARY TWO’S COMPLEMENT

TABLE II. Ideal Input Voltages and Output Codes.