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ADS8324EB Datasheet(PDF) 9 Page - Texas Instruments |
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ADS8324EB Datasheet(HTML) 9 Page - Texas Instruments |
9 / 14 page ADS8324 9 SBAS172A www.ti.com SYMBOL DESCRIPTION MIN TYP MAX UNITS tSMPL Analog Input Sample Time 4.5 5.0 Clk Cycles tCONV Conversion Time 16 Clk Cycles tCYC Throughput Rate 50 kHz tCSD CS Falling to 0 ns DCLOCK LOW tSUCS CS Falling to 50 ns DCLOCK Rising thDO DCLOCK Falling to 5 20 ns Current DOUT Not Valid tdDO DCLOCK Falling to Next 100 250 ns DOUT Valid tdis CS Rising to DOUT Tri-State 50 100 ns ten DCLOCK Falling to DOUT 100 200 ns Enabled tf DOUT Fall Time 50 150 ns tr DOUT Rise Time 75 200 ns FIGURE 5. ADS8324 Basic Timing Diagrams. DIGITAL INTERFACE SIGNAL LEVELS The CMOS digital output (DOUT) will swing from 0V to VCC. If VCC is 3V, and this output is connected to a 5V CMOS logic input, then that IC may require more supply current than normal and may have a slightly longer propaga- tion delay. SERIAL INTERFACE The ADS8324 communicates with microprocessors and other digital systems via a synchronous 3-wire serial inter- face, as shown in Figure 5 and Table I. The DCLOCK signal synchronizes the data transfer with each bit being transmit- ted on the falling edge of DCLOCK. Most receiving systems will capture the bitstream on the rising edge of DCLOCK. However, if the minimum hold time for DOUT is acceptable, the system can use the falling edge of DCLOCK to capture each bit. A falling CS signal initiates the conversion and data transfer. The first 4.5 to 5.0 clock periods of the conversion cycle are used to sample the input signal. After the fifth falling DCLOCK edge, DOUT is enabled and will output a LOW value for one clock period. For the next 16 DCLOCK periods, DOUT will output the conversion result, most sig- nificant bit first followed by two zeros on clock cycles 15 and 16. After the two zero “dummy bits” have been output, subsequent clocks will repeat the output data but in a least significant bit first format starting with a zero. CS must be taken HIGH following a conversion in order to place DOUT in tri-state. Subsequent clocks will have no effect on the converter. A new conversion is initiated only when CS has been taken HIGH and returned LOW. DATA FORMAT The output data from the ADS8324 is in Binary Two’s Complement format, as shown in Table II. This table repre- sents the ideal output code for the given input voltage and does not include the effects of offset, gain error, or noise. TABLE I. Timing Specifications (VCC = 1.8V) –40°C to +85 °C. See Figure 6 for test conditions. CS/SHDN D OUT DCLOCK Complete Cycle Power Down Conversion Sample Use positive clock edge for data transfer t SUCS t CONV t SMPL NOTE: Minimum 22 clock cycles required for 14-bit conversion. Shown are 24 clock cycles. If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again. B13 (MSB) B12 B11 B10 B9 B8 B7 B6 B0 (LSB) 00 B5 B4 B3 B1 B2 Hi-Z 0 Hi-Z t CSD DESCRIPTION ANALOG VALUE Full-Scale Range 2 • VREF Least Significant 2 • VREF/16384 Bit (LSB) BINARY CODE HEX CODE +Full Scale +VREF – 1 LSB 0111 1111 1111 1100 7FFC Midscale 0V 0000 0000 0000 0000 0000 Midscale – 1LSB 0V – 1 LSB 1111 1111 1111 1100 FFFC –Full Scale –VREF 1000 0000 0000 0000 8000 DIGITAL OUTPUT BINARY TWO’S COMPLEMENT TABLE II. Ideal Input Voltages and Output Codes. |
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