ADS8383

SLAS005B – DECEMBER 2002 – REVISED MAY 2003

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6

TIMING CHARACTERISTICS

All specifications typical at –40

°C to 85°C, +VA = +VBD = 5 V (see Notes 1, 2, and 3)

PARAMETER

MIN

TYP

MAX

UNIT

tCONV

Conversion time

1.5

µs

tACQ

Acquisition time

0.4

µs

tpd1

CONVST low to conversion started (BUSY high)

10

50

ns

tpd2

Propagation delay time, End of conversion to BUSY low

10

20

ns

tw1

Pulse duration, CONVST low

40

ns

tsu1

Setup time, CS low to CONVST low

20

ns

tw2

Pulse duration, CONVST high

20

ns

CONVST falling edge jitter

10

ps

tw3

Pulse duration, BUSY signal low

Min(tACQ)

1

µs

tw4

Pulse duration, BUSY signal high

1.52

µs

th1

Hold time, First data bus data transition (RD low, or CS low for read cycle, or BYTE or

BUS18/16 input changes) after CONVST low

40

ns

td1

Delay time, CS low to RD low

0

ns

tsu2

Setup time, RD high to CS high

0

ns

tw5

Pulse duration, RD low time

50

ns

ten

Enable time, RD low (or CS low for read cycle) to data valid

20

ns

td2

Delay time, data hold from RD high

5

ns

td3

10

20

ns

tw6

RD high

20

ns

th2

Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge

125

ns

tpd4

Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge

Max(td5)

ns

td4

Delay time, BYTE edge to BUS18/16 edge skew

0

ns

tsu3

Setup time, BYTE or BUS18/16 rising edge to RD falling edge

10

ns

th3

Hold time, BYTE or BUS18/16 falling edge to RD falling edge

10

ns

tdis

Disable time, RD High (CS high for read cycle) to 3-stated data bus

20

ns

td5

Delay time, BUSY low to MSB data valid

30

ns

tsu4

Setup time, BYTE or BUS18/16 change before BUSY falling edge

10

20

µs

(1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.

(2) See timing diagrams.

(3) All timing are measured with 20 pF equivalent loads on all data bits and BUSY pins.