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ICE2PCS05 Datasheet(PDF) 10 Page - Infineon Technologies AG |
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ICE2PCS05 Datasheet(HTML) 10 Page - Infineon Technologies AG |
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10 / 20 page  CCM-PFC ICE2PCS05/G Functional Description Version 1.2 10 22 Mar 2010 3.6 Average Current Control 3.6.1 Complete Current Loop The complete system current loop is shown in Figure 11. Figure 11 Complete System Current Loop It consists of the current loop block which averages the voltage at pin ISENSE, resulted from the inductor current flowing across R1. The averaged waveform is compared with an internal ramp in the ramp generator and PWM block. Once the ramp crosses the average waveform, the comparator C1 turns on the driver stage through the PWM logic block. The Nonlinear Gain block defines the amplitude of the inductor current. The following sections describe the functionality of each individual blocks. 3.6.2 Current Loop Compensation The compensation of the current loop is done at the ICOMP pin. This is the OTA2 output and a capacitor C3 has to be installed at this node to ground (see Figure 11). Under normal mode of operation, this pin gives a voltage which is proportional to the averaged inductor current. This pin is internally shorted to 4.2V in the event of IC shuts down when OLP and UVLO occur. 3.6.3 Pulse Width Modulation (PWM) The IC employs an average current control scheme in continuous conduction mode (CCM) to achieve the power factor correction. Assuming the voltage loop is working and output voltage is kept constant, the off duty cycle D OFF for a CCM PFC system is given as From the above equation, D OFF is proportional to VIN. The objective of the current loop is to regulate the average inductor current such that it is proportional to the off duty cycle D OFF, and thus to the input voltage V IN. Figure 12 shows the scheme to achieve the objective. Figure 12 Average Current Control in CCM The PWM is performed by the intersection of a ramp signal with the averaged inductor current at pin 5 (ICOMP). The PWM cycle starts with the Gate turn off for a duration of T OFFMIN (250ns typ.) and the ramp is kept discharged. The ramp is then allowed to rise after T OFFMIN expires. The off time of the boost transistor ends at the intersection of the ramp signal and the averaged current waveform. This results in the proportional relationship between the average current and the off duty cycle D OFF. Figure 13 shows the timing diagrams of T OFFMIN and the PWM waveforms. Figure 13 Ramp and PWM waveforms 3.6.4 Nonlinear Gain Block The nonlinear gain block controls the amplitude of the regulated inductor current. The input of this block is the R S ICE2PCS05/G Vout L1 C2 R3 R4 Gate Driver D1 From Full-wave Retifier GATE R1 R2 OTA2 ICOMP 4.2V Current Loop Compensation Current Loop Nonlinear Gain 1.0mS +/-50uA (linear range) C3 S2 Fault ISENSE C1 PWM Comparator PWM Logic Q Input From Voltage Loop voltage proportional to averaged Inductor current R7 D OFF V IN V OUT -------------- = t ave(I IN) at ICOMP ramp profile GATE drive T OFFMIN 2.5% of T V CREF (1) V RAMP PWM ramp released PWM cycle (1) V CREF is a function of VICOMP t |
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