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CAT5411BI-00-TE13 Datasheet(PDF) 1 Page - Catalyst Semiconductor |
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CAT5411BI-00-TE13 Datasheet(HTML) 1 Page - Catalyst Semiconductor |
1 / 16 page 1 DESCRIPTION The CAT5411 is two Digitally Programmable Potentiometers (DPPs™) integrated with control logic and 16 bytes of NVRAM memory. Each DPP consists of a series of 63 resistive elements connected between two externally accessible end points. The tap points between each resistive element are connected to the wiper outputs with CMOS switches. A separate 6-bit control register (WCR) independently controls the wiper tap switches for each DPP. Associated with each wiper control register are four 6-bit non-volatile memory data registers (DR) used for storing up to four wiper settings. Writing to the CAT5411 Dual Digitally Programmable Potentiometers (DPP™) with 64 Taps and SPI Interface FEATURES s Two linear-taper digitally programmable potentiometers s 64 resistor taps per potentiometer s End to end resistance 2.5k Ω, 10kΩ, 50kΩ or 100kΩ s Potentiometer control and memory access via SPI interface: Mode (0, 0) and (1, 1) s Low wiper resistance, typically 80 Ω Ω Ω Ω Ω s Nonvolatile memory storage for up to four wiper settings for each potentiometer s Automatic recall of saved wiper settings at power up s 2.5 to 6.0 volt operation s Standby current less than 1 µA s 1,000,000 nonvolatile WRITE cycles s 100 year nonvolatile memory data retention s 24-lead SOIC, 24-lead TSSOP, and BGA s Industrial temperature ranges PIN CONFIGURATION FUNCTIONAL DIAGRAM © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Document No. 2114, Rev. G wiper control register or any of the non-volatile data registers is via a SPI serial bus. On power-up, the contents of the first data register (DR0) for each of the two potentiometers is automatically loaded into its respective wiper control register. The CAT5411 can be used as a potentiometer or as a two terminal, variable resistor. It is intended for circuit level or system level adjustments in a wide variety of applications. BGA Top View - Bump Side Down W1 W0 H0 H1 R R L0 L1 R R WIPER CONTROL REGISTERS NONVOLATILE DATA REGISTERS SPI BUS INTERFACE CONTROL LOGIC SCK SI WP A0 A1 R R CS SO ALO GEN FR TM LEAD FREE 1 2 3 4 A B C D E F RW0 CS A1 RL1 RL0 WP SI RW1 VCC RH0 RH1 VSS NC NC NC NC NC SO HOLD NC NC A0 SCK NC 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 CAT 5411 VCC RL0 RH0 RW0 CS WP SI A1 RL1 RH1 RW1 GND NC NC NC NC A0 SO HOLD SCK NC NC NC NC 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 CAT 5411 SI A1 RL1 RH1 RW1 GND NC NC NC NC SCK HOLD WP CS RW0 RH0 RL0 VCC NC NC NC NC A0 SO SOIC Package (J, W)TSSOP Package (U, Y) |
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