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MC100EP016FAR2 Datasheet(PDF) 5 Page - ON Semiconductor

Part # MC100EP016FAR2
Description  ECL 8-Bit Synchronous Binary Up Counter
Download  15 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC100EP016FAR2 Datasheet(HTML) 5 Page - ON Semiconductor

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MC10EP016, MC100EP016
http://onsemi.com
5
Table 4. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
W
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
Pb-Free Pkg
LQFP-32
QFN-32
Level 2
N/A
Level 2
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Transistor Count
897 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 5. MAXIMUM RATINGS)
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
VI  VCC
VI  VEE
6
-6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
-40 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
qJA
Thermal Resistance (Junction-to-Ambient)
0 lfpm
500 lfpm
32 LQFP
32 LQFP
80
55
°C/W
°C/W
qJC
Thermal Resistance (Junction-to-Case)
Standard Board
32 LQFP
12 to 17
°C/W
qJA
Thermal Resistance (Junction-to-Ambient)
0 lfpm
500 lfpm
QFN-32
QFN-32
31
27
°C/W
°C/W
qJC
Thermal Resistance (Junction-to-Case)
(Note 2)
QFN-32
12
°C/W
Tsol
Wave Solder
Pb
Pb-Free
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with y8 filled thermal vias under exposed pad.


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