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BD8325FVT

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TSZ22111・15・001

TSZ02201-0Q3Q0AJ83250-1-2

●Description of Blocks

①

Internal Power Supply

This is a regulator for powering the internal circuits via VCC. There is no direct output pin from this block.

②

LDO Block

This is the 5V regulator that can provide the power supply for startup block. It should be bypassed by 0.1uF~0.47uF for

stability. The circuit is utilized for the pull-up power supply of FB pin and the power supply for SAWOSC, CLK and SS/SD

block. UVLO function is built-in (4.5V Typ). Once UVLO signal is detected, OUT, AUX, OUT2F and OUT2R pins turn L,

and the capacitor connected to SS/SD pin is also discharged instantaneously. The short current between VREF and

GND is 12mA (Typ).

③

UVLO block

This is UVLO detection circuit of VCC, LINE and LDO.

The IC starts up and shuts down based on the sequence on timing chart.

When LINE UVLO signal is reset, 5uA current flows through LINEUV pin while when LINE UVLO is detected, the current

is 0uA. It is possible to adjust the HYS value through the external resistor. Moreover, VCC and VREF’s UVLO

comparators have built-in minimum of 2us noise filters for avoiding error detection.

④

Timing Set Block

For simplicity of application, the adjustable function can be achieved through external resistor:

・

switching timing of OUT, AUX, OUT2F and OUT2R pin

→ resistors connected from RDELON, RDELOFF1, RDELOFF2, RDELSLF, RDELSLR pin (1.6V typ) to ground

・

oscillator frequency and MAX Duty

→ resistors connected from RTON and RTOFF pin (1.6V typ) to ground

・

slope compensation amplitude

→ resistor connected from RSLP pin (maximum value of sawtooth wave: 2.5V (typ)) to ground

There is a built-in open detection function such that when it is activated, the outputs are terminated. This is to avoid the

pin opening caused by the incorrect mounting of external resistor.

⑤

Synchronization CLK transmitter

When multiple ICs will be use, the synchronization function is implemented so that the frequency remains synchronous.

The master IC provides CLKOUT signal to the slave IC through SYNC pin, and in turn, the slave IC and master IC’s

frequency can be synchronized. The transmitter includes the I/O part of CLK and SYNC pin. By means of extracting the

frequency (at the rising edge) only, the MaxDuty can be set. There is H-side and L-side resistors connected to CLKOUT

pin with a value of 0.6kΩ.

⑥

SAWOSC block

The circuit is used for generating clock, duty and slope signal. In the stand-alone operation (external synchronization

inactivated) the voltage of SAWH pin, which determines the amplitude of internal triangular wave, is 2.65V (typ). During

the external synchronization operation, the internal circuits control the SAWH voltage to synchronize with the external

clock. LVP circuit is applied to SAWH pin, and the detection and reset voltage are 1.35V (typ) and 2.6V (typ). As soon as

SAWH LVP signal is detected, OUT, AUX, OUT2F and OUT2R turn L and SS/SD is discharged instantaneously, and

SAWH is pre-charged (10kΩ).

⑦

Feedback block

The voltage of SS/SD from block ⑪ is compared with FB voltage; the lower voltage enters the PWM signal generator.

⑧

CS1, CS2 control block

This is the block intended for OCP detection.

When CS1 exceeds 0.48V, OCP1 signal is produced and RESET flag of Latch circuit (⑫) is activated. In addition,

OUT=L, AUX=L, OUT2F=L, OUT2R=H and the power transfer from input to output is terminated momentarily. When the

CLK enters into next cycle, the power transfer starts again. As the new cycle starts, the low-side NMOS switch connected

to CS1 pin is ON when CLKOUT=H in order to make sure that the reset signal is removed. With the series of action,

pulse-by-pulse mode OCP protection is observed as shown in the example application design.

When CS2 voltage exceeds 1.2V (typ), OCP2 signal is detected, the IC enters into SOFT_STOP mode and SS/SD pin

starts to be discharged with 15uA current. As CS2 voltage drops to 1.2V (typ) and SS/SD≦ 0.5V, the IC returns to

SOFT_START mode and starts up. Like CS1, the low side NMOS switch connected to CS2 is ON when CLKOUT=H. As

shown in the example application design, if the output is shorted to ground, then the SOFT_START mode and

SOFT_STOP mode alternate, the chip’s HICCUP OCP protection operates.