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PCA9518D Datasheet(PDF) 2 Page - NXP Semiconductors |
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PCA9518D Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 12 page Philips Semiconductors Product data sheet PCA9518 Expandable 5-channel I2C hub 2 2004 Sep 29 DESCRIPTION The PCA9518 is a BiCMOS integrated circuit intended for application in I2C and SMBus systems. While retaining all the operating modes and features of the I2C system, it permits extension of the I2C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus enabling virtually unlimited buses of 400 pF. The I2C-bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the PCA9518 enables the system designer to divide the bus into an unlimited number of segments off of a hub where any segment to segment transition sees only one repeater delay and is multiple master capable on each segment. Using multiple PCA9518 parts, any width hub (in multiples of five)1 can be implemented using the expansion pins. A PCA9518 cluster cannot be put in series with a PCA9515/16 or with another PCA9518 cluster. Multiple PCA9518 devices can be grouped with other PCA9518 devices into any size cluster thanks to the EXPxxxx pins that allow the I2C signals to be sent/received from/to one PCA9518 to/from another PCA9518 within the cluster. Since there is no direction pin, slightly different “legal” low voltage levels are used to avoid lock up conditions between the input and the output of individual repeaters in the cluster. A “regular low” applied at the input of any of the PCA9518 devices will then be propagated as a “buffered low” with a slightly higher value to all enabled outputs in the PCA9518 cluster. When this “buffered low” is applied to a PCA9515 and PCA9516 or separate PCA9518 cluster (not connected via the EXPxxx pins) in series, the second PCA9515 and PCA9516 or PCA9518 cluster will not recognize it as a “regular low” and will not propagate it as a “buffered low ” again. The PCA9510/9511/9513/9514 and PCA9512 cannot be used in series with the PCA9515 and PCA9516 or PCA9518 but can be used in series with themselves since they use shifting instead of static offsets to avoid lock up conditions. FEATURES • Expandable 5 channel, bi-directional buffer • I2C-bus and SMBus compatible • Active-HIGH individual repeater enable inputs • Open-drain input/outputs • Lock-up free operation • Supports arbitration and clock stretching across the repeater • Accommodates standard mode and fast mode I2C devices and multiple masters • Powered-off high-impedance I2C pins • Operating supply voltage range of 3.0 V to 3.6 V • 5 V tolerant I2C and enable pins • 0 kHz to 400 kHz clock frequency2 • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101. • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA. • Package offerings: SO and TSSOP PIN CONFIGURATION 10 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 EXPSCL1 EXPSCL2 SCL0 SDA0 SCL1 SDA1 EN1 SCL2 SDA2 GND VCC EN4 SDA4 SCL4 EN3 SDA3 SCL3 EXPSDA2 EN2 EXPSDA1 SU01595 Figure 1. Pin configuration PIN DESCRIPTION PIN SYMBOL FUNCTION 1 EXPSCL1 Expandable serial clock pin 1 2 EXPSCL2 Expandable serial clock pin 2 3 SCL0 Serial clock bus 0 4 SDA0 Serial data bus 0 5 SCL1 Serial clock bus 1 6 SDA1 Serial data bus 1 7 EN1 Active-HIGH Bus 1 enable Input 8 SCL2 Serial clock bus 2 9 SDA2 Serial data bus 2 10 GND Supply ground 11 EN2 Active-HIGH Bus 2 enable Input 12 SCL3 Serial clock bus 3 13 SDA3 Serial data bus 3 14 EN3 Active-HIGH Bus 3 enable Input 15 SCL4 Serial clock bus 4 16 SDA4 Serial data bus 4 17 EN4 Active-HIGH Bus 4 enable Input 18 EXPSDA1 Expandable serial data pin 1 19 EXPSDA2 Expandable serial data pin 2 20 VCC Supply power ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DRAWING NUMBER 20-pin plastic SO –40 °C to +85 °C PCA9518D PCA9518D SOT163-1 20-pin plastic TSSOP –40 °C to +85 °C PCA9518PW PCA9518 SOT360-1 Standard packing quantities and other packaging data is available at www.standardproducts.philips.com/packaging. 1. Only four ports per device are available if individual Enable is required. 2. The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater. |
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