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BD8303MUV

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www.rohm.com

TSZ22111・15・001

TSZ02201-0Q3Q0NZ00320-1-2

16.Feb.2015 Rev.002

Description of Blocks

1. VREF

This block generates ERROR AMP reference voltage. The reference voltage is set to 1.0V.

2. VREG

This is a voltage regulator block which outputs 5.0V and is used as power supply for IC internal circuit and BOOT pin

supply. Follows power supply voltage when 5.0V or below while the output voltage drops at the same time.

An external 1.0µF capacitor is recommended to prevent oscillation.

3. UVLO

This block prevents the malfunction of the internal circuitry during start-up or when the supply drops below a certain

voltage. When VREG is below 2.4V, the HG1, HG2, LG1 and LG2 pin is low, this block turns OFF all FET and DC/DC

converter outputs and resets the timer latch of the internal SCP circuit and soft-start circuit

4. SCP

This block is the Short Circuit Protection that uses a Timer Latch System. It has an internal counter that is in synch with

OSC. When the INV pin is set to 1.0V or lower voltage, the internal counter will count about 8200 pulses after which the

or the supply voltage will reset the latch circuit.

5. OSC

The OSC block generates the internal frequency of the IC. The frequency can be varied depending on the value of the

6. ERROR AMP

The ERROR AMP block detects output signals and PWM control signals and compares them with an internal reference

voltage set at 1.0V.

7.

PWM COMP

The PWM COMP block is a Voltage-to-Pulse Width converter that controls the output voltage depending on the input

voltage. This block controls the pulse width by comparing the internal SLOPE waveform with the ERROR AMP output

voltage. The output signal of the PWM COMP block is then fed to the driver. Max Duty and Min Duty are set at the

primary side and the secondary side of the inductor respectively, which are as follows:

Primary side (SW1)

HG1 Max Duty

:

About 90%,

HG1 Min Duty

:

0 %

Secondary side (SW2)

LG2 Max Duty

:

About 90%,

LG2 Min Duty

:

About 10%,

8. SOFT START

This block prevents in-rush current during start-up by bringing the output voltage of the DCDC converter into a soft-start.

The Soft-Start block is in synch with the internal OSC block. This block enables the output voltage of the DCDC

9. N-Channel DRIVER

This block consists of a CMOS inverter circuit that drives the built-in N-Channel FET. It provides dead time for preventing

feed through during switching of HG1 = L to LG1 = H to HG2 = L to LG2 = H and LG1 = L to HG1 = H, LG2 = L to HG2 =

H. The dead time is set at about 100nsec for each individual SWs

10. ON/OFF LOGIC

This block enables and disables the IC depending on the voltage applied at STB pin (Pin 5). The IC Turns ON when STB

voltage is 2.5 V or higher and it Turns OFF when STB is open or when 0V is applied. The STB pin has a pull-down

resistor of approximately 400

kΩ.