Datasheet

Datasheet

5/38

TSZ02201-0J3J0AL01130-1-2

21.Apr.2016 Rev.001

BD90521MUV-C / BD90521EFV-C

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www.rohm.com

TSZ22111 • 15 • 001

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TSD (Thermal Shut Down)

This is an overheat protection circuit. In order to prevent IC thermal destruction/runaway, output is turned off when chip

temperature rises to about 150°C or higher. It is recovered when temperature returns to constant temperature. However,

since overheat protection circuit is essentially built-in for the purpose of protection of IC itself, carry out thermal design to

keep chip temperature below about 150°C as TSD detection temperature.

・

This is an overcurrent protection circuit. When output Pch POWER MOS FET is turned on and voltage between drain and

source exceeds internal reference voltage value, overcurrent protection activates. This overcurrent protection is self-reset

type. When overcurrent protection activates, duty becomes small and output voltage is reduced. However, since these

protection circuits are effective in protection from destruction due to sudden accidents, avoid using them when continuous

protection circuit is in action.

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SCP (Short Current Protection)

This is a load short-circuit protection circuit. When the state of output of 60% or lower is detected in oscillation cycle × 256

(s), POWER MOS FET is turned off. If output voltage is recovered to 60% or higher before completion of 256 cycles,

POWER MOS FET is not turned off. This load short-circuit protection is cancelled after retention of oscillation cycle × 2048

(s), and it is restarted with soft start. Elongation of off time results in decrease of mean output current. During startup of

power source, this function is masked until output reaches set voltage to prevent startup failure.

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UVLO (Under Voltage Lock-Out)

This is a low voltage wrong operation prevention circuit. It prevents wrong operation of internal circuits during power

source voltage startup and when power source voltage is reduced. Power source voltage is monitored and when it is

reduced to 2.25 V (Typ) or lower, output POWER MOS FET is turned off. When UVLO is cancelled, it is restarted with soft

start. This threshold has hysteresis of 100 mV (Typ).

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VOLTAGE REFERENCE

It supplies reference voltage to internal circuits.

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OVP

When output voltage is detected to have exceeded set value + 10%, Pch FET and Nch FET of output is turned off. After

detection, when output is reduced and the overvoltage state is cancelled, switching action is restarted. There is hysteresis

of 2% in overvoltage detection voltage and cancel voltage.

・

PGOOD

When output voltage is below 90% or above 110% of set value, output error state is assumed, and PGOOD terminal is

turned “Low”. There is hysteresis of 2% in detection voltage and cancel voltage. At the time of EN OFF and when UVLO

and TSD are in action, PGOOD terminal output is also turned “Low”. If VIN input voltage exceeds 2 V, PGOOD output

becomes effective. Since output is open drain type, connect pull up to VIN or an external power source with resistance of

10kΩ - 100 kΩ.