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DLP6500BFLQ Datasheet(PDF) 7 Page - Texas Instruments |
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DLP6500BFLQ Datasheet(HTML) 7 Page - Texas Instruments |
7 / 50 page 7 DLP6500 www.ti.com DLPS040A – OCTOBER 2014 – REVISED OCTOBER 2016 Product Folder Links: DLP6500 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated (1) The following power supplies are required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be connected. PIN TYPE (I/O/P) SIGNAL DESCRIPTION NAME(1) NO. VBIAS N5, P4, R3, R5 Power Analog Supply voltage for positive Bias level of Micromirror reset signal. VOFFSET G1, J1, L1, N1, R1 Power Analog Supply voltage for HVCMOS logic. Supply voltage for stepped high voltage at Micromirror address electrodes. Supply voltage positive Offset level of Micromirror reset signal. VRESET A3, A5, B4, C7 Power Analog Power supply for negative reset level of mirror reset signal VCC A7, A15, C1 Power Analog Supply voltage for LVCMOS core logic. E1, U1, AB2 Power Analog Supply voltage for normal high level at Micromirror address electrodes. AC9, AC15 Power Analog Supply voltage for positive Offset level of Micromirror reset signal during Power Down sequence. VCCI A21, A27, D30, M30, Y30, AC21, AC27 Power Analog Power supply for LVDS Interface VSS A1, A9, B8, B14, B20, B26, B30, C13, C19, C25, D6, D18, D24, E29, F2, F28, G27, H4, H26, J3, J25, K2, K30, L25, L27, L29, M2, M6, M26, M28, N25, N29, P30, R25, T2, T26, U27, V28, V30, W5, W29, Y4, Y12, Y18, Y24, AA3, AA9, AA13, AA19, AA25, AB14, AB20, AB26, AB30 Power Analog Device Ground. Common return for all power. |
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