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OMAP3530ECBB72 Datasheet(PDF) 2 Page - Texas Instruments |
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OMAP3530ECBB72 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 265 page  OMAP3530, OMAP3525 SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013 www.ti.com Associative) • Luma and Chroma Separate Video (S- Video) – 16-KB Data Cache (4-Way Set-Associative) – Rotation 90-, 180-, and 270-Degrees – 256-KB L2 Cache – Resize Images From 1/4x to 8x • 112KB of ROM – Color Space Converter • 64KB of Shared SRAM – 8-Bit Alpha Blending • Endianess: • Serial Communication – ARM Instructions – Little Endian – 5 Multichannel Buffered Serial Ports – ARM Data – Configurable (McBSPs) – DSP Instruction and Data - Little Endian • 512-Byte Transmit and Receive Buffer • External Memory Interfaces: (McBSP1, McBSP3, McBSP4, and – SDRAM Controller (SDRC) McBSP5) • 16- and 32-Bit Memory Controller with • 5-KB Transmit and Receive Buffer 1GB of Total Address Space (McBSP2) • Interfaces to Low-Power Double Data • SIDETONE Core Support (McBSP2 and Rate (LPDDR) SDRAM McBSP3 Only) For Filter, Gain, and Mix • SDRAM Memory Scheduler (SMS) and Operations Rotation Engine • Direct Interface to I2S and PCM Device – General Purpose Memory Controller (GPMC) and TDM Buses • 16-Bit-Wide Multiplexed Address and • 128-Channel Transmit and Receive Mode Data Bus – Four Master or Slave Multichannel Serial • Up to 8 Chip-Select Pins with 128-MB Port Interface (McSPI) Ports Address Space per Chip-Select Pin – High-, Full-, and Low-Speed USB OTG • Glueless Interface to NOR Flash, NAND Subsystem (12- and 8-Pin ULPI Interface) Flash (with ECC Hamming Code – High-, Full-, and Low-Speed Multiport USB Calculation), SRAM, and Pseudo-SRAM Host Subsystem • Flexible Asynchronous Protocol Control • 12- and 8-Pin ULPI Interface or 6-, 4-, and for Interface to Custom Logic (FPGA, 3-Pin Serial Interface CPLD, ASICs, and so forth) • Supports Transceiverless Link Logic • Nonmultiplexed Address and Data Mode (TLL) (Limited 2-KB Address Space) – One HDQ™/1-Wire® Interface • System Direct Memory Access (sDMA) – Three UARTs (One with Infrared Data Controller (32 Logical Channels with Association [IrDA] and Consumer Infrared Configurable Priority) [CIR] Modes) • Camera Image Signal Processor (ISP) – Three Master and Slave High-Speed Inter- – CCD and CMOS Imager Interface Integrated Circuit (I2C) Controllers – Memory Data Input • Removable Media Interfaces: – BT.601 (8-Bit) and BT.656 (10-Bit) Digital – Three Multimedia Card (MMC)/Secure Digital YCbCr 4:2:2 Interface (SD) with Secure Data I/O (SDIO) – Glueless Interface to Common Video • Comprehensive Power, Reset, and Clock Decoders Management – Resize Engine – SmartReflex™ Technology • Resize Images From 1/4x to 4x – Dynamic Voltage and Frequency Scaling • Separate Horizontal and Vertical Control (DVFS) • Display Subsystem • Test Interfaces – Parallel Digital Output – IEEE 1149.1 (JTAG) Boundary-Scan • Up to 24-Bit RGB Compatible • HD Maximum Resolution – ETM Interface • Supports Up to 2 LCD Panels – Serial Data Transport Interface (SDTI) • Support for Remote Frame Buffer • 12 32-Bit General-Purpose Timers Interface (RFBI) LCD Panels • 2 32-Bit Watchdog Timers – 2 10-Bit Digital-to-Analog Converters (DACs) • 1 32-Bit 32-kHz Sync Timer Supporting: • Up to 188 General-Purpose I/O (GPIO) Pins • Composite NTSC and PAL Video (Multiplexed with Other Device Functions) 2 OMAP3530 and OMAP3525 Applications Processors Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OMAP3530 OMAP3525 |
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