SN65LVDS31 Logic Diagram (Positive Logic)

4Z

4Y

3Z

3Y

2Z

2Y

1Z

1Y

13

14

11

10

5

6

3

2

4A

3A

2A

1A

G

G

15

9

7

1

12

4

Logic Symbol

SN65LVDS31

4Z

4Y

3Z

3Y

2Z

2Y

1Z

1Y

4A

3A

2A

1A

G

G

13

14

11

10

5

6

3

2

15

9

7

1

12

4

≥ 1

EN

This symbol is in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12.

SN65LVDS31-EP

SLLSE91

– SEPTEMBER 2011

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERABLE PART

TOP-SIDE MARKING

VID NUMBER

NUMBER

–55°C to 125°C

SOIC-D

SN65LVDS31MDREP

LVDS31EP

V62/07627-01XE

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2)

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

xxx

2

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Copyright

© 2011, Texas Instruments Incorporated

Product Folder Link(s): SN65LVDS31-EP