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BD9B400MUV-E2 Datasheet(PDF) 2 Page - Rohm |
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BD9B400MUV-E2 Datasheet(HTML) 2 Page - Rohm |
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2 / 34 page  2/30 © 2016 ROHM Co., Ltd. All rights reserved. www.rohm.com TSZ22111 • 15 • 001 BD9B400MUV TSZ02201-0J3J0AJ01200-1-2 22.Apr.2016 Rev.002 Pin Configuration(s) Pin Description(s) Pin No. Pin Name Function 1, 2 PVIN Power supply terminals for the switching regulator. These terminals supply power to the output stage of the switching regulator. Connecting a 22µF ceramic capacitor is recommended. 3, 4 PGND Ground terminals for the output stage of the switching regulator. 5 AGND Ground terminal for the control circuit. 6 FB An inverting input node for the error amplifier and main comparator. See page 22 for how to calculate the resistance of the output voltage setting. 7 FREQ Terminal for setting switching frequency. Connecting this terminal to ground makes switching to operate constant on-time corresponding to 2.0MHz. Connecting this terminal to AVIN makes switching to operate constant on-time corresponding to 1.0MHz. Please fix this terminal to AVIN or ground in operation. 8 MODE Terminal for setting switching control mode. Connecting this terminal to AVIN forces the device to operate in the fixed frequency PWM mode. Connecting this terminal to ground enables the Deep-SLLM control and the mode is automatically switched between the Deep-SLLM control and fixed frequency PWM mode. Please fix this terminal to AVIN or ground in operation. 9 SS Terminal for setting the soft start time. The rise time of the output voltage can be specified by connecting a capacitor to this terminal. See page 23 for how to calculate the capacitance. 10, 11, 12 SW Switch nodes. These terminals are connected to the source of the High-Side MOSFET and drain of the Low-Side MOSFET. Connect a bootstrap capacitor of 0.1 µF between these terminals and BOOT terminal. In addition, connect an inductor of 0.47µH to 1µH (FREQ=L), 1μH to 1.5μH (FREQ=H) considering the direct current superimposition characteristic. 13 BOOT Terminal for bootstrap. Connect a bootstrap capacitor of 0.1 µF between this terminal and SW terminals. The voltage of this terminal is the gate drive voltage of the High-Side MOSFET. 14 PGD A “Power Good” terminal, an open drain output. Use of pull up resistor is needed. See page 17 for how to specify the resistance. When the FB terminal voltage reaches more than 80% of 0.8 V, the internal Nch MOSFET turns off and the output turns High. 15 EN Enable terminal. Turning this terminal signal Low (0.8V or lower) forces the device to enter the shutdown mode. Turning this terminal signal High (2.0V or higher) enables the device. This terminal must be terminated. 16 AVIN Terminal for supplying power to the control circuit of the switching regulator. Connecting a 0.1µF ceramic capacitor is recommended. This terminal must be connected to PVIN. - E-Pad A backside heat dissipation exposed pad. Connecting to the internal PCB ground plane by using multiple vias provides excellent heat dissipation characteristics. Figure 2. Pin Assignment (TOP VIEW) PGND 4 1 2 3 PVIN PGND SS 9 12 11 10 SW 13 16 15 14 5 6 7 8 SW SW PVIN E-Pad |
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