Electronic Components Datasheet Search |
|
S3C1850 Datasheet(PDF) 5 Page - Samsung semiconductor |
|
S3C1850 Datasheet(HTML) 5 Page - Samsung semiconductor |
5 / 91 page S3C1840 1-4 PIN CONFIGURATION (20 DIP, 20 SOP) VSS XI XO P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P3.3 S3C1840 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD P2.0/REM TEST P2.1 P2.2 P2.3 P2.4 P3.0 P3.1 P3.2 Figure 1-3. Pin Configuration (20 DIP, 20 SOP) Table 1-2. Pin Description for 20 Pins Pin Name Pin Number Pin Type Description I/O Circuit Type P0.0-P0.3 4, 5, 6, 7 Input 4-bit input port when P2.13 is low A P1.0-P1.1 8, 9 Input 2-bit input port when P2.13 is high A P2.0/REM 19 Output 1-bit individual output for remote carrier frequency (1) B P2.2-P2.4 16, 15, 14 Output 1-bit individual output port C P2.1 17 D P3.0-P3.3 13, 12, 11, 10 Output 4-bit parallel output port C TEST 18 Input Input pin for test (Normally connected to V SS) – X I 2 Input Oscillation clock input – X O 3 Output Oscillation clock output – V DD 20 – Power supply – V SS 1 – Ground – NOTES: 1. The carrier can be selected by software as fxx/12 (1/3 duty), fxx/12 (1/4 duty), fxx/8 (1/2 duty), or no-carrier frequency. 2 Package type can be selected as 20 DIP, or 20 SOP in the ordering sheet. |
Similar Part No. - S3C1850 |
|
Similar Description - S3C1850 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |