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QL4016-4CF100M Datasheet(PDF) 2 Page - List of Unclassifed Manufacturers |
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QL4016-4CF100M Datasheet(HTML) 2 Page - List of Unclassifed Manufacturers |
2 / 18 page 2 www.quicklogic.com © 2002 QuickLogic Corporation • • • • • • QL4016 QuickRAM Data Sheet Rev I Architecture Overview The QuickRAM family of ESPs (Embedded Standard Products) offers FPGA logic in combination with Dual-Port SRAM modules. The QL4016 is a 16,000 usable PLD gate member of the QuickRAM family of ESPs. QuickRAM ESPs are fabricated on a 0.35 µm four-layer metal process using QuickLogic's patented ViaLinkTM technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. The QL4016 contains 320 logic cells and 10 Dual Port RAM modules (see Figure 1). Each RAM module has 1,152 RAM bits, for a total of 11,520 bits. RAM Modules are Dual Port (one read port, one write port) and can be configured into one of four modes: 64 (deep) × 18 (wide), 128 × 9, 256 × 4, or 512 × 2 (see Figure 4). With a maximum of 82 I/Os, the QL4016 is available in 84-pin PLCC, 100-pin TQFP, 100-pin CQFP and 144-pin TQFP packages. Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules (see Figure 2). This approach allows up to 512-deep configurations as large as 16 bits wide in the smallest QuickRAM device and 44 bits wide in the largest device. Software support for the complete QuickRAM family, including the QL4016, is available through two basic packages. The turnkey QuickWorksTM package provides the most complete ESP software solution from design entry to logic synthesis, to place and route, to simulation. The QuickTools package provides a solution for designers who use Cadence, Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Aldec, or other third-party tools for design entry, synthesis, or simulation. The QuickLogicTM variable grain logic cell features up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fan- in of 29 including register and control lines (see Figure 3). Figure 2: QuickRAM Module Bits RDATA WDATA RADDR RDATA WADDR WDATA RAM Module (1,152 bits) RAM Module (1,152 bits) |
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