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MC100EL17 Datasheet(PDF) 4 Page - ON Semiconductor |
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MC100EL17 Datasheet(HTML) 4 Page - ON Semiconductor |
4 / 5 page MC100EL17 www.onsemi.com 4 Table 6. AC CHARACTERISTICS (VCC = 5.0 V; VEE = 0 V or VCC = 0 V; VEE = −5.0 V (Note 1)) −40°C 25°C 85°C Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit fMAX Maximum Toggle Frequency 1.75 GHz tPLH tPHL Propagation Delay Differential D to Q Single-Ended 330 280 530 580 350 300 550 600 360 310 560 610 ps tSKEW Skew Output-to-Output (Note 2) Part-to-Part (Diff) (Note 2) Duty Cycle (Diff) (Note 3) 75 200 25 75 200 25 75 200 25 ps tJITTER Random Clock Jitter (RMS) 0.7 ps VPP Input Swing (Note 4) 150 1000 150 1000 150 1000 mV tr tf Output Rise/Fall Times Q (20% − 80%) 280 550 280 550 280 550 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. VEE can vary +0.8 V / −0.5 V. 2. Skews are valid across specified voltage range, part-to-part skew is for a given temperature. 3. Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device. 4. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈ 40. Figure 2. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) Driver Device Receiver Device QD Q D Zo = 50 W Zo = 50 W 50 W 50 W VTT VTT = VCC − 3.0 V Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices |
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