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MC74HC4046ADTG Datasheet(PDF) 6 Page - ON Semiconductor

Part # MC74HC4046ADTG
Description  Phase-Locked Loop
Download  15 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC74HC4046ADTG Datasheet(HTML) 6 Page - ON Semiconductor

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MC74HC4046A
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6
DETAILED CIRCUIT DESCRIPTION
Voltage Controlled Oscillator/Demodulator Output
The VCO requires two or three external components to
operate. These are R1, R2, C1. Resistor R1 and Capacitor C1
are selected to determine the center frequency of the VCO
(see typical performance curves Figure 15). R2 can be used
to set the offset frequency with 0 volts at VCO input. For
example, if R2 is decreased, the offset frequency is
increased. If R2 is omitted the VCO range is from 0 Hz. The
effect of R2 is shown in Figure 25, typical performance
curves. By increasing the value of R2 the lock range of the
PLL is increased and the gain (volts/Hz) is decreased. Thus,
for a narrow lock range, large swings on the VCO input will
cause less frequency variation.
Internally, the resistors set a current in a current mirror, as
shown in Figure 6. The mirrored current drives one side of
the capacitor. Once the voltage across the capacitor charges
up to Vref of the comparators, the oscillator logic flips the
capacitor which causes the mirror to charge the opposite side
of the capacitor. The output from the internal logic is then
taken to VCO output (Pin 4).
The input to the VCO is a very high impedance CMOS
input and thus will not load down the loop filter, easing the
filters design. In order to make signals at the VCO input
accessible without degrading the loop performance, the
VCO input voltage is buffered through a unity gain Op−amp
to Demod Output. This Op−amp can drive loads of 50K
ohms or more and provides no loading effects to the VCO
input voltage (see Figure 13).
An inhibit input is provided to allow disabling of the VCO
and all Op−amps (see Figure 6). This is useful if the internal
VCO is not being used. A logic high on inhibit disables the
VCO and all Op−amps, minimizing standby power
consumption.
Figure 5. Logic Diagram for VCO
_
+
_
+
_
+
I1
I2
R2
12
VREF
VCOIN
R1
9
11
10
5
6
7
4
++
Vref
C1
(EXTERNAL)
DEMODOUT
CURRENT
MIRROR
I1 + I2 = I3
VCOOUT
INH
I3


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