MC100EP196

http://onsemi.com

4

Table 2. CONTROL PIN

Pin

State

Function

EN

LOW (Note 3)

Input Signal is Propagated to the Output

HIGH

Output Holds Logic Low State

LEN

LOW (Note 3)

Transparent or LOAD mode for real time delay values present on D[0:10].

HIGH

LOCK and HOLD mode for delay values on D[0:10]; further changes on D[0:10]

are not recognized and do not affect delay.

SETMIN

LOW (Note 3)

Output Delay set by D[0:10]

HIGH

Set Minimum Output Delay

SETMAX

LOW (Note 3)

Output Delay set by D[0:10]

HIGH

Set Maximum Output Delay

D10

LOW

CASCADE Output LOW, CASCADE Output HIGH

HIGH

CASCADE Output LOW, CASCADE Output High

3. Internal pulldown resistor will provide a logic LOW if pin is left unconnected.

Table 3. CONTROL D[0:10] INTERFACE

Pin

State

Function

ECL Mode

No Connect

LVCMOS Mode

1.5 V

$ 100 mV

LVTTL Mode (Note 5)

is 2.2 k

Table 4. DATA INPUT ALLOWED OPERATING VOLTAGE MODE TABLE

POWER SUPPLY

CONTROL DATA SELECT INPUTS PINS (D [0:10])

LVCMOS

LVTTL

LVPECL

LVNECL

PECL Mode Operating Range

YES

YES

YES

N/A

NECL Mode Operating Range

N/A

N/A

N/A

YES