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MC100EPT21DR2G Datasheet(PDF) 2 Page - ON Semiconductor |
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MC100EPT21DR2G Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 9 page MC100EPT21 http://onsemi.com 2 1 2 3 45 6 7 8 Q GND VCC Figure 1. Logic Diagram and 8−Lead Pinout (Top View) D NC D VBB NC LVTTL LVPECL Table 1. PIN DESCRIPTION PIN Q D*, D* Differential LVPECL/LVDS/CML Input FUNCTION LVTTL/LVCMOS Output VCC VBB Output Reference Voltage Positive Supply GND Ground NC No Connect * Pin will default to 1/2 of VCC when left open. EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Elec- trically connect to the most negative supply (GND) or leave unconnected, floating open. Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor D 50 kW Internal Input Pulldown Resistor D 50 kW Internal Input Pullup Resistor D, D 50 kW ESD Protection Human Body Model Machine Model Charged Device Model > 1.5 kV > 100 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) SOIC−8 TSSOP−8 DFN8 Level 1 Level 3 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 81 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. |
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