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MAX6441UTC Datasheet(PDF) 8 Page - Maxim Integrated Products |
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MAX6441UTC Datasheet(HTML) 8 Page - Maxim Integrated Products |
8 / 14 page has stabilized before power-converter or microproces- sor activity is enabled. These devices also have an independent µP supervisor that monitors VCC and provides an active-low reset out- put. A manual reset function is available to allow the user to reset the µP with a push-button. Low-Battery Output The low-battery outputs are available in active-low (LBO, LBOL, LBOH, LBOLH), open-drain configura- tions. The low-battery outputs can be pulled to a volt- age independent of VCC or VBATT, up to 5.5V. This allows the device to monitor and operate from direct battery voltage while interfacing to higher voltage microprocessors. The MAX6439/MAX6440 single-output voltage monitors provide a single low-battery output, LBO. These fixed- threshold devices assert LBO when VBATT drops below VLTH and remain asserted for at least 150ms after VBATT rises above VHTH (see Figure 2). The MAX6441/ MAX6442 triple-output voltage monitors provide three low-battery outputs: LBOH, LBOL, and LBOLH. LBOH asserts when VBATT drops below VHTH- and remains asserted for at least 150ms after VBATT rises above VHTH+. LBOL asserts when VBATT drops below VLTH- and remains asserted for at least 150ms after VBATT rises above VLTH+. LBOLH asserts when VBATT drops below VLTH- and remains asserted for at least 150ms after VBATT rises above VHTH+ (see Figure 3). For fast- rising VBATT input, the LBOL timeout period must com- plete before the LBOH/LBOLH timeout period begins. Reset Output The MAX6439–MAX6442 provide an active-low reset output (RESET). RESET is asserted when the voltage at VCC falls below the reset threshold level. Reset remains asserted for the reset timeout period after VCC exceeds the threshold. If VCC goes below the reset threshold before the reset timeout period is completed, the inter- nal timer restarts. The MAX6439/MAX6441 have open- drain reset outputs, while the MAX6440/MAX6442 have push-pull reset outputs (see Figure 4). Low-Power, Single-/Dual-Level Battery Monitors with Hysteresis and Integrated µP Reset 8 _______________________________________________________________________________________ 5% HYST LTH DETECT VTH DETECT 5% HYST HTH DETECT VBATT VCC 1.23V LBO TIMEOUT PERIOD RESET TIMEOUT PERIOD VCC LBOL LBOH LBOLH RESET MR MAX6441 Figure 1b. Functional Diagram MAX6440 LTH DETECT HTH DETECT R S Q LBO TIMEOUT PERIOD RESET TIMEOUT PERIOD VTH DETECT VCC VCC VBATT LBO RESET VCC 1.23V Q MR Figure 1a. Functional Diagram |
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