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PL602082UMG Datasheet(PDF) 7 Page - Micrel Semiconductor |
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PL602082UMG Datasheet(HTML) 7 Page - Micrel Semiconductor |
7 / 15 page Micrel, Inc. PL60208X December 11, 2013 7 Revision 1.1 hbwhelp@micrel.com or (408) 955-1690 AC Electrical Characteristics (4, 6) VDD = VDDO1/2 = 3.3V 5% or 2.5V 5% VDD = 3.3V 5%, VDDO1/2 = 3.3V 5% or 2.5V 5% TA = 40C to 85C. RL = 50Ω to VSS Symbol Parameter Condition Min. Typ. Max. Units TR/TF HCSL output rise/fall time 20% - 80% 150 300 450 ps ODC Output duty cycle 48 50 52 % TSKEW Output-to-output skew Note 7 45 ps TLOCK PLL lock time 20 ms Tjit() RMS phase jitter (8) 100MHz or 125MHz Integration range (12kHz – 20MHz) Integration range (10kHz – 1.5MHz) Integration range (1.5MHz – Nyquist) 200MHz or 250MHz Integration range (12kHz – 20MHz) Integration range (10kHz – 1.5MHz) Integration range (1.5MHz – Nyquist) 254 220 142 253 222 112 fs Notes: 2. Exceeding the absolute maximum ratings may damage the device. 3. The device is not guaranteed to function outside its operating ratings. 4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. 5. Specification for packaged product only 6. All phase noise measurements were taken with an Agilent 5052B phase noise system. 7. Defined as skew between outputs at the same supply voltage and with equal load conditions; Measured at the output differential crossing points. 8. Measured using 25MHz crystal as the input reference source. If using an external reference input, use a low phase noise source. With an external reference, the phase noise will follow the input source phase noise up to about 1MHz. |
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