Wide Input Voltage, Synchronous USB Buck Regulator

with Remote Load Regulation

A8652,

A8653

4

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Package LP, 16-Pin eTSSOP Pinout Diagram

Terminal List Table

Symbol

Number

Function

EN

1

Enable input. This pin is used to turn the converter on or off: set this pin high to turn the converter on or set this pin low to

turn the converter off. May be connected to VIN.

VIN

2

Power input for the control circuits and the drain of the internal high-side N-channel MOSFET. A high quality ceramic

capacitor should be placed very close to this pin.

SS

3

the hiccup period during overcurrent.

GADJ

4

This pin is used to set the gain of the differential current sense amplifier with ISEN+/ISEN– pins. A resistor from this pin

to GND set the amplifier gain. Together with load sense resistor, it sets the desired voltage correction at the specified

load condition. Grounding GADJ disables Remote Load Regulation function.

FB

5

pin to program the output voltage.

IADJ

6

Active current limit adjust pin. A resistor from this pin to GND sets the current limit. When the load current exceeds this

limit, the output voltage will decrease at the predefined slope.

SGND

7

Signal (quiet) GND.

COMP

8

Output of the error amplifier and compensation node for the control loop. Connect a series RC network from this pin to

GND for loop compensation.

SYNC/FSET

9

POK

10

Power OK output signal. This pin is an open-drain output that transitions from low impedance to high impedance when

the output is within the final regulation voltage and no load side current limit exists.

ISEN–

11

Negative current-sensing pin to the internal current sense amplifier, connected to the load side of the external current

sensing resistor.

ISEN+

12

Positive current-sensing pin to the internal current sense amplifier, connected to the inductor side of the external current

sensing resistor.

PGND

13, 14

Power GND.

SW

115

placed as close as possible to this pin and connected with relatively wide traces.

BOOT

16

High-side gate drive boost input. Connect a 100 nF ceramic capacitor from BOOT to SW.

PAD

–

Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the ground

plane(s) of the PCB with at least 6 vias, directly in the pad.

PAD

16

1

EN

BOOT

15

2

VIN

SW

14

3

SS

PGND

13

4

GADJ

PGND

12

5

FB

ISEN+

11

6

IADJ

ISEN–

10

7

SGND

POK

9

8

COMP

SYNC/FSET

PINOUT DIAGRAM AND TERMINAL LIST TABLE