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PL102-10SC-R Datasheet(PDF) 3 Page - Micrel Semiconductor |
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PL102-10SC-R Datasheet(HTML) 3 Page - Micrel Semiconductor |
3 / 7 page PL102-10 Low Skew Output Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 2/5/09 Page 3 3. Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Input/Output Frequency t1 2.5V/3.3V 15 145/170 MHz Duty Cycle DC Measured at VDD/2, CL=15pF, Fout = 100MHz 45 50 55 % Rise Time Tr Measured between 10% and 90%VDD, CL=15pF 1.2 1.5 ns Fall Time Tf Measured between 90% and 10%, CL=15pF 1.2 1.5 ns Output to Output Skew Tskew All outputs equally loaded, CL=15pF 200 ps Delay, REF Rising Edge to CLKOUT Rising Edge Tdelay Measured at VDD/2 0 350 ps Device to Device Skew Tdsk-dsk Measured at VDD/2 on the CLKOUT pins of devices 0 700 ps Cycle to Cycle Jitter Tcyc-cyc Measured at 100MHz 60 ps PLL Lock Time Tlock Stable power supply, valid clock presented on REF pin 1.0 ms Jitter; Absolute Jitter Tjabs Measured 10,000 cycles, low jitter input signal 20 50 ps Jitter; 1-sigma Tj1-s Measured 10,000 cycles, low jitter input signal 9 15 ps SWITCHING WAVEFORMS Duty Cycle Timing t1 t2 VDD/2 VDD/2 VDD/2 Output - Output Skew VDD/2 VDD/2 T SKEW Output Output |
Similar Part No. - PL102-10SC-R |
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Similar Description - PL102-10SC-R |
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