MSP50C601

MIXED-SIGNAL PROCESSOR

SPSS029A – SEPTEMBER 2000 – REVISED FEBRUARY 2001

1

POST OFFICE BOX 655303

for High-Quality Sound.

12 MIPS)

Speech (Using 1.57 Mb of Onboard

Program + Data ROM)

Algorithms Such as MELP, CELP, LPC,

ADPCM, and Polyphonic Music

Capabilities

Hand-Held Devices.

Three Batteries

Than 10

µA in Deep-Sleep Mode

– 24 General Purpose Bit Configurable I/O

– 8 Inputs With Programmable Pullup

Resistor And a Dedicated Interrupt

(Key-Scan)

Interrupt Service

Crystal Reference Oscillator

and Diagnostics

100-Pin PJM Package.

Ceramic Package for Development

description

The MSP50C601 is a low-cost, mixed-signal processor that combines a speech synthesizer, general-purpose

I/O, onboard ROM, and direct speaker drive in a single package. The computational unit utilizes a powerful new

DSP which gives the MSP50C601 unprecedented speed and computational flexibility compared with previous

devices of its type. The MSP50C601 supports a variety of speech and audio coding algorithms, providing a

range of options for speech duration and sound quality.

The device consists of a micro-DSP core, embedded program, and data memory, and a self-contained clock

generation system. General-purpose periphery is comprised of 32 bits of partially configurable I/O.

The core processor is a general-purpose 16-bit microcontroller with DSP capability. The basic core block

includes computational unit (CU), data address unit, program address unit, two timers, eight level interrupt

processor, and several system and control registers. The core processor gives the MSP50C601 break-point

capability in emulation.

The processor is Harvard type for efficient DSP algorithm execution. It requires separate program and data

memory blocks to permit simultaneous access. The ROM has a protection scheme to prevent third-party

pirating. It is configured in 32K 17-bit words.

The total ROM space is divided into three areas: 1) The lower 2K words are reserved by Texas Instruments for

a built-in self-test 2) The upper 30K words are for user program/data 3) An additional 1 Mb data ROM provides

for up to 24 minutes of speech.

The data memory is internal static RAM. The RAM is configured in 640 17-bit words. All memories are designed

to consume minimum power at a given system clock and algorithm acquisition frequency.

Copyright

 2001, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.