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FEDL7204-003-02 Datasheet(PDF) 8 Page - LAPIS Semiconductor Co., Ltd. |
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FEDL7204-003-02 Datasheet(HTML) 8 Page - LAPIS Semiconductor Co., Ltd. |
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8 / 214 page  FEDL7204-003-02 ML7204-003 8/214 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Analog power supply voltage AVDD — –0.3 to +4.6 V Digital power supply voltage DVDD — –0.3 to +4.6 V Analog input voltage VAIN Analog pin –0.3 to AVDD+0.3 V VDIN1 Normal digital pin –0.3 to DVDD+0.3 V DVDD = 3.0 to 3.6 V –0.3 to +6.0 V Digital input voltage VDIN2 5 V tolerant pin DVDD < 3.0 V –0.3 to DVDD+0.3 V Output current IO — –20 to +20 mA Power dissipation PD Ta = 60 C, per package 350 mW Storage temperature Tstg — –65 to +150 C RECOMMENDED OPERATING CONDITIONS (AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = –20 to 60 C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Analog power supply voltage AVDD — 3.0 3.3 3.6 V Digital power supply voltage DVDD — 3.0 3.3 3.6 V Operating temperature range Ta — –20 — +60 C VIH1 Normal digital pin 0.75 DVDD — DVDD+ 0.3 V Digital high-level input voltage VIH2 5 V tolerant pin 0.75 DVDD — 5.5 V Digital low-level input voltage VIL Digital pin –0.3 — 0.19 DVDD V Digital input rise time tIR Digital pin — 2 20 ns Digital input fall time tIF Digital pin — 2 20 ns Digital output load capacitance CDL Digital pin — — 50 pF Digital output load resistance RDL Pull-up resistance, PCMO 500 — — AVREF bypass capacitor Cvref Between AVREF-AGND 2.2+0.1 — 4.7+0.1 F VREGOUT bypass capacitor Cvout Between VREGOUT-DGND — 10+0.1 — F VBG bypass capacitor CVBG Between VBG-DGND — 150 — pF Master clock frequency Fmck MCK –0.01% 12.288 +0.01% MHz PCM shift clock frequency Fbclk BCLK (at input) 64 ( 0.1%) — 2048 ( 0.1%) kHz PCM synchronous signal frequency Fsync SYNC (at input) –0.1% 8.0 +0.1% kHz Clock duty ratio DRCLK MCK, BCLK (at input) 40 50 60 % tBS BCLK to SYNC (at input) 100 — — ns PCM synchronous timing tSB SYNC to BCLK (at input) 100 — — ns PCM synchronous signal width tWS SYNC (at input) 1BCLK — 100 s (Note) On power-on/shut-down sequence For the analog power supply voltage (AVDD) and the digital power supply voltage (DVDD) to be supplied to this LSI, it is recommended that power be applied to them simultaneously. However, if simultaneous power-up is difficult due to the power supply circuit configuration, power them up in the order of DVDD AVDD. The power supplies should be shut down in the reverse order of power-on sequence. |
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