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CDK8307AITQ80 Datasheet(PDF) 5 Page - Exar Corporation |
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CDK8307AITQ80 Datasheet(HTML) 5 Page - Exar Corporation |
5 / 31 page Data Sheet ©2009-2013 Exar Corporation 5/31 Rev 1C Pin Assignments - QFN Pin No. Pin Name Description QFN-64 49, 50, 57 AVDD Analog power supply, 1.8V 3, 6, 9, 37, 40, 43, 46 AVSS Analog ground 1 IP1 Positive differential input signal, channel 1 2 IN1 Negative differential input signal, channel 1 4 IP2 Positive differential input signal, channel 2 5 IN2 Negative differential input signal, channel 2 7 IP3 Positive differential input signal, channel 3 8 IN3 Negative differential input signal, channel 3 10 IP4 Positive differential input signal, channel 4 11 IN4 Negative differential input signal, channel 4 38 IP5 Positive differential input signal, channel 5 39 IN5 Negative differential input signal, channel 5 41 IP6 Positive differential input signal, channel 6 42 IN6 Negative differential input signal, channel 6 44 IP7 Positive differential input signal, channel 7 45 IN7 Negative differential input signal, channel 7 47 IP8 Positive differential input signal, channel 8 48 IN8 Negative differential input signal, channel 8 12, 14, 36 DVSS Digital ground 35 DVDD Digital and I/O power supply, 1.8V 13 PD Power-down input. Activate after applying power in order to initialize the ADC correctly. Alternatively use the SPI power down feature. 15 D1P LVDS channel 1, positive output 16 D1N LVDS channel 1, negative output 17 D2P LVDS channel 2, positive output 18 D2N LVDS channel 2, negative output 19 D3P LVDS channel 3, positive output 20 D3N LVDS channel 3, negative output 21 D4P LVDS channel 4, positive output 22 D4N LVDS channel 4, negative output 27 D5P LVDS channel 5, positive output 28 D5N LVDS channel 5, negative output 29 D6P LVDS channel 6, positive output 30 D6N LVDS channel 6, negative output 31 D7P LVDS channel 7, positive output 32 D7N LVDS channel 7, negative output 33 D8P LVDS channel 8, positive output 34 D8N LVDS channel 8, negative output 23 FCLKP LVDS frame clock (1x), positive output 24 FCLKN LVDS frame clock (1x), negative output 25 LCLKP LVDS bit clock, positive output |
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