SN74LVCE161284

19BIT IEEE 1284 TRANSLATION TRANSCEIVER

WITH ERRORFREE POWER UP

SCES541 − JANUARY 2004

5

POST OFFICE BOX 655303

−0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−2 V to 7 V

. . . . . . . . . . . . . . . . . .

Peripheral side (see Note 1)

. . . . . . . . . . .

−20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PERI LOGIC OUT

±100 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±200 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

65 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance,

70

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package

63

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The ac input-voltage pulse duration is limited to 40 ns if the amplitude is greater than −0.5 V.

3. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 4)

MIN

MAX

UNIT

VCC CABLE

Supply voltage for the cable side, VCC CABLE ≥ VCC

3

5.5

V

VCC

Supply voltage

3

3.6

V

A, B, DIR, and HD

2

VIH

High-level input voltage

C14−C17

2.3

V

VIH

High-level input voltage

HOST LOGIC IN

2.6

V

PERI LOGIC IN

2

A, B, DIR, and HD

0.8

VIL

Low-level input voltage

C14−C17

0.8

V

VIL

Low-level input voltage

HOST LOGIC IN

1.6

V

PERI LOGIC IN

0.8

VI

Input voltage

Peripheral side

0

VCC

V

VI

Input voltage

Cable side

0

5.5

V

VO

Open-drain output voltage

HD low

0

5.5

V

HD high, B and Y outputs

−14

IOH

High-level output current

A outputs and HOST LOGIC OUT

−4

mA

IOH

High-level output current

PERI LOGIC OUT

−0.5

mA

B and Y outputs

14

IOL

Low-level output current

A outputs and HOST LOGIC OUT

4

mA

IOL

Low-level output current

PERI LOGIC OUT

84

mA

TA

Operating free-air temperature

0

70

°C

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.