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HV9120NG-G-M901 Datasheet(PDF) 10 Page - Microchip Technology |
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HV9120NG-G-M901 Datasheet(HTML) 10 Page - Microchip Technology |
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10 / 18 page  HV9120/HV9123 DS20005519A-page 10 2016 Microchip Technology Inc. 5.0 DETAILED DESCRIPTION 5.1 High-Voltage Regulator The high-voltage regulator included in HV9120 and HV9123 consists of a high-voltage, n-channel, deple- tion-mode DMOS transistor, driven by an error ampli- fier, providing a current path between the VIN terminal and the VDD terminal. The maximum current, about 20 mA, occurs when VDD = 0, with current reducing as VDD rises. This path shuts off when VDD rises to somewhere between 7.8 and 9.4V. So, if VDD is held at 10 or 12V by an external source, no current other than leakage is drawn through the high voltage transistor. This mini- mizes dissipation. Use an external capacitor between VDD and GND to store energy used by the chip in the time between shut- off of the high voltage path and the VDD supply’s output rising enough to take over powering the chip. This capacitor should have a value of 100X or more the effective gate capacitance of the MOSFET being driven, as well as very good high-frequency character- istics. See the equation below. Ceramic caps work well. Electrolytic capacitors are generally not suitable. The device uses a resistor divider string to monitor VDD for both the under voltage lockout circuit and the shutoff circuit of the high voltage FET. Setting the under volt- age sense point about 0.6V lower on the string than the FET shutoff point guarantees that the under voltage lockout releases before the FET shuts off. 5.2 Bias Circuit HV9120 and HV9123 require an external bias resistor, connected between the BIAS pin and GND, to set cur- rents in a series of current mirrors used by the analog sections of the chip. The nominal external bias current requirement is 15 to 20 µA, which can be set by a 390 kΩ to 510 kΩ resistor if VDD = 10V, or a 510 kΩ to 680 kΩ resistor if VDD = 12V. A precision resistor is not required, ±5% meets the device requirements. 5.3 Clock Oscillator The clock oscillator of the HV9120 and HV9123 con- sists of a ring of CMOS inverters, timing capacitors, and a capacitor-discharge FET. A single external resistor between the OSCI and OSCO sets the oscillator fre- quency (see Figure 2-1, Output Switching Frequency vs Oscillator Resistance). HV9120 includes a frequency-dividing flip-flop that allows the part to operate with a 50% duty limit. Accord- ingly, the effective switching frequency of the power converter is half the oscillator frequency (see Figure 2- 1, Output Switching Frequency vs Oscillator Resis- tance). An internal, discharge FET resets the oscillator ramp at the end of the oscillator cycle. The FET is internally connected to GND in HV9120 (50% max duty version). Whereas, the FET is externally connected to GND, by way of a resistor, in the HV9123 (100% duty version). The resistor programs the oscillator dead time at the end of the oscillator period in HV9123 applications. The oscillator turns off during shutdown to reduce sup- ply current by about 150 μA. 5.4 Reference The reference of the HV9120 and HV9123 consists of a band-gap reference, followed by a buffer amplifier, which scales the voltage up to 4.0V. The scaling resis- tors of the buffer amplifier are trimmed during manufac- ture so that the output of the error amplifier, when connected in a gain of -1 configuration, is as close to 4.0V as possible. This nulls out the input offset of the error amplifier. As a consequence, even though the observed reference voltage of a specific part may not be exactly 4.0V, the feedback voltage required for proper regulation will be 4.0V. An approximately 50 kΩ resistor is located internally between the output of the reference buffer amplifier and the circuitry it feeds–reference output pin and non- inverting input to the error amplifier. This allows overrid- ing the internal reference with a low impedance voltage source ≤6.0V. Using an external reference reinstates the input offset voltage of the error amplifier. Overriding the reference should seldom be necessary. The reference of the HV9120 and HV9123 is a high impedance node, and usually there will be significant electrical noise nearby. Therefore, a bypass capacitor between the reference pin and GND is strongly recom- mended. The reference buffer amplifier is compen- sated to be stable with a capacitive load of 0.01 to 0.1 µF. 5.5 Error Amplifier The error amplifier in HV9120 and HV9123 is a low- power, differential-input, operational amplifier. A PMOS input stage is used, so the common mode range includes ground and the input impedance is high. 5.6 Current Sense Comparators HV9120 and HV9123 use a dual-comparator system with independent comparators for modulation and cur- rent limiting. This allows the designer greater latitude in compensation design, as there are no clamps, except ESD protection, on the compensation pin. CVDD 100 gate charge of FET at 10V |
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