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UT621024SC-35L Datasheet(PDF) 5 Page - List of Unclassifed Manufacturers

Part # UT621024SC-35L
Description  128K X 8 BIT LOW POWER CMOS SRAM
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UTRON
UT621024
Rev. 1.5
128K X 8 BIT LOW POWER CMOS SRAM
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
WRITE CYCLE 1 ( WE Controlled) (1,2,3,5)
Address
DOUT
High-Z
1
CE
WE
Data Valid
DIN
CE2
tCW2
tCW1
tAW
tWC
tWHZ
tWP
tAS
tOW
tDW
tDH
tWR
(4)
(4)
WRITE CYCLE 2 (
1
CE and CE2 Controlled) (1,2,5)
Address
DOUT
High-Z
1
CE
WE
(4)
Data Valid
DIN
CE2
tWC
tAS
tCW1
tAW
tCW2
tWR
tWP
tWHZ
tDW
tDH
Notes :
1.
WE or
1
CE must be HIGH or CE2 must be LOW during all address transitions.
2. A write occurs during the overlap of a low
1
CE , a high CE2 and a low
WE .
3. During a WE controlled with write cycle with OE LOW, tWP must be greater than tWHZ+tDW to allow the I/O drivers
to turn off and data to be placed on the bus.
4. During this period, I/O pins are in the output state, and input singals must not be applied.
5. If the
1
CE LOW transition occurs simultaneously with or after
WE LOW transition, the outputs remain in a high
impedance state.
6. tOW and tWHZ are specified with CL=5pF. Transition is measured ± 500mV from steady state.


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