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AP1016AEN Datasheet(PDF) 7 Page - Asahi Kasei Microsystems |
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AP1016AEN Datasheet(HTML) 7 Page - Asahi Kasei Microsystems |
7 / 15 page [AP1016AEN] MS1589-E-03 - 7 - 2014/12 Parameter Symbol Condition min typ max Unit Propagation delay time (“L”→”H”) tPDLH Load=1 k between OUTA and OUTB Refer to Figure 3(a) IN1A=IN2A=L IN1B=IN2B=200kHz 0.07 0.3 μs Propagation delay time (“H”→”L”) tPDHL 0.17 0.3 μs Propagation delay time (Hi-Z→”H”) tPDZH (Note 5)the time from 50% input to 90% output Refer to Figure 3(c) Guaranteed by design(Note 6) 0.1 0.3 μs Propagation delay time (“H”→ Hi-Z) tPDHZ (Note 5)the time from 50% input to 25% down output Refer to Figure 3(d) Guaranteed by design(Note 6) 0.1 0.3 μs Output pulse width tPW Load=20kΩ between OUTA and OUTB, Input puls width=1us,Refer to Figure 3(b) Guaranteed by design (Note 6) 0.7 1.09 1.5 μs Control logic Input High level voltage (IN1A, IN1B, IN2A, IN2B) VIH VC = 2.7V-5.5V 0.7×VC V Input Low level voltage (IN1A, IN1B, IN2A, IN2B) VIL 0.3×VC V Input High level voltage (IN1A, IN1B, IN2A, IN2B) IIH Vterm1 = 3.0V 9 15 21 μA Input Low level current (IN1A, IN1B, IN2A, IN2B) IIL VC = 2.7V-5.5V -1.0 μA Input pulse rise time (IN1A, IN1B, IN2A, IN2B) tr 1.0 μs Input pulse fall time (IN1A, IN1B, IN2A, IN2B) tf 1.0 μs Protection functions (Figure 4, Figure 5) VC low level detection voltage VCUV 1.9 2.2 2.5 V Voltage hysteresis VCUVHY S Guaranteed by design (Note 6) 0.02 0.05 0.1 V Thermal shut down temperature TTSD Guaranteed by design (Note 6) 150 175 200 C Temperature hysteresis TTSDHYS Guaranteed by design (Note 6) 20 30 40 C Note 5. 100k load resister is connected between VM and OUTA/B, and also between OUTA/B and GND. Note 6. Not tested in production. |
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