NB3F8L3005C

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3

Table 1. PIN DESCRIPTION

Number

Name

Type

Input

Default

Description

3, 5

Q0, Q1

LVCMOS

Outputs − Bank A

13, 15, 17

Q2, Q3, Q4

LVCMOS

Outputs − Bank B

2, 6

VDDOA

Power

Positive Supply Pins for Bank A Outputs Q0 − Q1

14, 18

VDDOB

Power

Positive Supply Pins for Bank B Outputs Q2 − Q4

1, 4, 7, 11,

12, 16, 19

GND

GND

Ground Supply

8, 23

VDD

Power

9

XTAL_IN

XTAL OSC / CLK Input

Crystal Oscillator Interface or External Clock Source at

LVCMOS Levels

10

XTAL_OUT

XTAL OSC Output

Crystal Interface

20

CLK

Diff / SE Input

Pullup /

Pulldown

Inverting differential clock input

21

CLK

Diff / SE Input

Pulldown

Non-inverting clock input

22

SEL

LVCMOS / LVTTL

Input

Pulldown

Input clock select. See Table 3 for function. Input Pulldown

24

OE

LVCMOS / LVTTL

Input

Pulldown

Output Enable Control. See Table 4 for function.

−

EP

−

The Exposed Pad (EP) on the QFN−24 package bottom is

thermally connected to the die for improved heat transfer out

of package. The exposed pad must be attached to a heat−

sinking conduit. The pad is electrically connected to the die,

and must be electrically connected to GND.

with 0.01

mF CAP to GND.

Table 2. PIN CHARACTERISTICS

Symbol

Parameter

Min

Typ

Max

Unit

Input Capacitance

4

pF

Input Pullup Resistor

50

k

W

Input Pulldown Resistor

50

k

W

Power Dissipation Capacitance (per output)

VDDO = 3.3 V

VDDO = 2.5 V

VDDO = 1.8 V

VDDO = 1.5 V

pF

Output Impedance

VDDO = 3.3 V

VDDO = 2.5 V

VDDO = 1.8 V

VDDO = 1.5 V

20

W