NB3H5150-01 datasheet(6/19 Pages) ONSEMI

Part #	NB3H5150-01

Description	2.5V / 3.3V Low Noise Multi-Rate Clock Generator

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Manufacturer	ONSEMI [ON Semiconductor]

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NB3H5150−01

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6

become effective and will begin to output the

selected frequencies.

2. Subsequent changes to any FS pin(s) will cause

the associated CLK(n) output(s) to momentarily

go to static levels, and then to resume at the new

frequency; CLK(n) will follow the FS(n) pin

programmable Tables 3 and 4 for output

frequencies and interface levels.

Note that in changing from LVPECL to LVCMOS

(or vice−versa), output logic levels cannot be

guaranteed. This is because the receiver inputs are

not likely to change in a given application, and the

LVPECL output loading in the application will

also not change. It is logical to presume that the

output type will be predetermined and fixed.

Therefore, in a system/application, the user should

be aware that subsequent change to the FS pin

should only change frequency, and not output type.

3. Power off/on cycle will repeat the entire sequence

4. Power Down

To initiate the Power−Down mode, the SDA pin

must be LOW and remain LOW. If the SCL/PD

pin is taken HIGH at any time, the device enters a

complete power−down mode with a current

consumption of less than 1 mA for the entire

device. When SCL/PD is subsequently taken

LOW, the device will function as though power

were removed and re−applied. That is, sequencing

will begin at #1.

Power−down is also available via I2C with a

register file.

FS(n) Pin Programmable Selection of Output Frequencies and Levels

Table 3. NB3H5150−01MNTXG − CLK1A:3A & CLK1B:3B OUTPUT FREQUENCY

SELECT TABLE WITH 25 MHz CRYSTAL

Logic Level

FS1 (CLK1)

(MHz)

FS2 (CLK2)

(MHz)

FS3 (CLK3)

(MHz)

Low

156.25 (LVPECL)

Mid / Float*

25.00 (LVPECL)

100.00 (LVPECL)

125.00 (LVPECL)

High

50.00 (LVPECL)

125.00 (LVPECL)

50.00 (LVPECL)

*(Default)

Table 4. NB3H5150−01MNTXG − CLK4A & CLK4B OUTPUT FREQUENCY

SELECT TRUTH TABLE (MHz) WITH 25 MHz CRYSTAL*

FS4A

FS4B

CLK4 (MHz)

Divider Type

Low

33.33 (LVCMOS)

Integer

Low

Mid / Float

66.66 (LVCMOS)

Fractional

Low

High

133.33 (LVCMOS)

Fractional

Mid / Float

Low

133.33 (LVPECL)

Fractional

Mid / Float*

156.25 (LVPECL)

Integer

Mid / Float

High

125.00 (LVPECL)

Integer

High

Low

25.00 (LVPECL)

Integer

High

Mid / Float

100.00 (LVPECL)

Integer

High

161.1328 (LVPECL)

Fractional

*(Default)

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