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IDT72V3632 Datasheet(PDF) 11 Page - Integrated Device Technology |
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IDT72V3632 Datasheet(HTML) 11 Page - Integrated Device Technology |
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11 / 29 page  11 COMMERCIAL TEMPERATURERANGE IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 FIFO WRITE/READ OPERATION The state of the port A data (A0-A35) outputs is controlled by port A Chip Select ( CSA) and port A Write/Read select (W/RA). The A0-A35 outputs are in the high-impedance state when either CSA or W/RA is HIGH. The A0-A35 outputs are active when both CSA and W/RA are LOW. Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH , MBA is LOW, and FFA/IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs by a LOW-to-HIGH transition of CLKA when CSAisLOW,W/RAisLOW,ENA is HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 2). FIFO reads and writes on port A are independent of any concurrent port B operation. Write and Read cycle timing diagrams for Port A can be found in Figure 4 and 7. TheportBcontrolsignalsareidenticaltothoseofportAwiththeexception thattheportBWrite/Readselect( W/RB)istheinverseoftheportAWrite/Read select(W/ RA).ThestateoftheportBdata(B0-B35)outputsiscontrolledbythe port B Chip Select ( CSB) and port B Write/Read select (W/RB). The B0-B35 outputs are in the high-impedance state when either CSB is HIGH or W/RB is LOW. The B0-B35 outputs are active when CSBisLOWandW/RBisHIGH. Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is LOW, and FFB/IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs byaLOW-to-HIGHtransitionofCLKBwhen CSBisLOW,W/RBisHIGH,ENB is HIGH, MBB is LOW, and EFB/ORBisHIGH(seeTable3).FIFOreadsand writes on port B are independent of any concurrent port A operation. Write and Read cycle timing diagrams for Port B can be found in Figure 5 and 6. The setup and hold time constraints to the port Clocks for the port Chip SelectsandWrite/Readselectsareonlyforenablingwriteandreadoperations andarenotrelatedtohigh-impedancecontrolofthedataoutputs.Ifaportenable is LOW during a clock cycle, the port’s Chip Select and Write/Read select may change states during the setup and hold time window of the cycle. WhenoperatingtheFIFOinFWFTmodeandtheOutputReadyflagisLOW, the next word written is automatically sent to the FIFO’s output register by the LOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflagHIGH. When the Output Ready flag is HIGH, subsequent data is clocked to the output registers only when a read is selected using the port’s Chip Select, Write/Read select, Enable, and Mailbox select. When operating the FIFO in IDT Standard mode, the first word will cause the Empty Flag to change state on the second LOW-to-HIGH transition of the Read Clock. The data word will not be automatically sent to the output register. Instead, data residing in the FIFO's memory array is clocked to the output register only when a read is selected using the port’s Chip Select, Write/Read select, Enable, and Mailbox select. SYNCHRONIZED FIFO FLAGS Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve flag signal reliability by reducing the probability of metastable events when CLKA and CLKB operate asynchronously to one another. EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA. EFB/ORB, AEB, FFB/IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2. EMPTY/OUTPUT READY FLAGS ( EFA/ORA, EFB/ORB) These are dual purpose flags. In the FWFT mode, the Output Ready (ORA, ORB) function is selected. When the Output Ready flag is HIGH, CSB W/RB ENB MBB CLKB Data B (B0-B35) I/O Port Function H X X X X High-Impedance None L L L X X Input None LL H L ↑ Input FIFO2 write LL H H ↑ Input Mail2 write L H L L X Output None LH H L ↑ Output FIFO1 read L H L H X Output None LH H H ↑ Output Mail1 read (set MBF1 HIGH) TABLE 3 PORT B ENABLE .UNCTION TABLE TABLE 2 PORT A ENABLE .UNCTION TABLE CSA W/ RA ENA MBA CLKA Data A (A0-A35) I/O Port Function H X X X X High-Impedance None L H L X X Input None LH H L ↑ Input FIFO1 write LH H H ↑ Input Mail1 write L L L L X Output None LL H L ↑ Output FIFO2 read L L L H X Output None LL H H ↑ Output Mail2 read (set MBF2 HIGH) |
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