Datasheet

Datasheet

11/36

TSZ02201-0F1F0C100250-1-2

© 2013 ROHM Co., Ltd. All rights reserved.

15.Feb.2016 Rev.003

www.rohm.com

TSZ22111・15・001

BD9489F

○Pin 13: DIMOUT

This is the output pin for external dimming NMOS. The table below shows the rough output

logic of each operation state, and the output H level is REG58. Please refer to “3.5 Timing

Chart” for detailed explanations, because DIMOUT logic has an exceptional behavior.

of LED current, as PWM turns from low to high.

Status

DIMOUT output

Normal

Same logic to PWM

Abnormal

GND Level

○Pin 14: GATE

This is the output terminal for driving the gate of the boost MOSFET. The high level

is REG58. Frequency can be set by the resistor connected to RT. Refer to <RT> pin description for the frequency setting.

When PWM=L, IC holds the OVP voltage at the edge of PWM=H to L, and operates to hold the adjacent voltage. Please

refer to section “3.5 Timing Chart”.

When PWM=L, IC outputs the necessary boost pulse to startup or to keep the output voltage. Please refer to section “2.8

The Retaining Function of The Output Voltage”.

As the retaining of the output voltage is enable, the GATE pulse is not output at the boundary of PWM logic such as High

to Low, or as Low to High.

Figure16. The GATE waveform as PWM dimming

As the retaining of the output voltage is disable, the GATE pulse is synchronized with the timing of PWM=L -> H

○Pin 15: CS

The CS pin has two functions.

1. DC / DC current mode Feedback terminal

This voltage compared to the voltage set by error amplifier controls the output

pulse.

2. Inductor current limit (OCP) terminal

The CS terminal also has an over current protection (OCP). If the voltage is more

than 0.4V(typ.), the switching operation will be stopped compulsorily. And the

next boost pulse will be restarted to normal frequency.

In addition, the CS voltage is more than 1.0V(typ.) during four GATE clocks, IC

will be latch off. As above OCP operation, if the current continues to flow

nevertheless GATE=L because of the destruction of the boost MOS, IC will stops

the operation completely.

Both of the above functions are enabled after 300ns (typ) when GATE pin

asserts high, because the Leading Edge Blanking function (LEB) is included

into this IC to prevent the effect of noise.

Please refer to section “3.3.1 OCP Setting / Calculation Method for the Current Rating of DCDC Parts”, for detailed

explanation.

If the capacitance Cs in the right figure is increased to a micro order, please be careful that the limited value of NMOS

drain current Id is more than the simple calculation. Because the current Id flows not only through Rcs but also through

Cs, as the CS pin voltage moves according to Id.

○Pin 16: REG58

And this terminal is also used as timer for discharging DCDC output capacitor.

Please refer to section“3.2.2 Shutdown Method and REG58 Capacitance Setting”, for detailed explanation.

Figure 15. DIMOUT terminal circuit

example

Figure 17. CS terminal circuit example