6.42

IDT70V9279/69S/L

High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

10

Timing Waveform of Read Cycle for Flow-through Output

Timing Waveform of Read Cycle for Pipelined Output

An

An + 1

An + 2

An + 3

ADDRESS

CLK

OE

Qn

Qn + 1

Qn + 2

3743 drw 06

(1)

(1)

(1)

(1)

(2)

UB, LB

(5)

An

An + 1

An + 2

An + 3

ADDRESS

CLK

UB, LB

(4)

OE

Qn

Qn + 1

Qn + 2

3743 drw 07

(1)

(1)

(1)

(2)

(5)

(1 Latency)

(6)

(6)

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.

are for reference use only.