ISP1104W datasheet(11/19 Pages) PHILIPS

Part #	ISP1104W

Description	Advanced Universal Serial Bus transceiver

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Manufacturer	PHILIPS [NXP Semiconductors]

Direct Link	http://www.nxp.com

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11 / 19 page

Philips Semiconductors

ISP1104

Advanced USB transceiver

Product data

Rev. 02 — 14 October 2003

11 of 19

9397 750 11229

[1]

VOH(min) =Vreg(3.3) − 0.2 V.

[2]

Includes external resistors of 33

Ω±1 % on both pins D+ and D−.

[3]

This voltage is available at pins Vreg(3.3) and Vpu(3.3).

[4]

The minimum voltage is 2.7 V in the suspend mode.

12. Dynamic characteristics

Capacitance

CIN

transceiver capacitance

pin to GND

-

20

pF

Resistance

ZDRV

driver output impedance

steady-state drive

[2] 34

39

44

Ω

ZINP

input impedance

10

-

M

Ω

RSW

internal switch resistance at

pin Vpu(3.3)

--10

Ω

Termination

VTERM

termination voltage for

upstream port pull-up (Rpu)

[3][4] 3.0

-

3.6

V

Table 13:

Static characteristics: analog I/O pins D

+ and D−…continued

VCC(5.0) = 4.0 V to 5.5 V; VGND =0V; Tamb = −40 °Cto +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 14:

Dynamic characteristics: analog I/O pins D

+ and D−

VCC(5.0) = 4.0 V to 5.5 V; VCC(I/O) = 1.65 V to 3.6 V; VGND =0V; Tamb = −40 °Cto +85 °C; see Figure 8; unless otherwise

speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Driver characteristics

tFR

rise time

CL = 50 pF to 125 pF;

10%to90% of

|VOH − VOL|;

see Figure 4

4

-

20

ns

tFF

fall time

CL = 50 pF to 125 pF;

90%to10% of

|VOH − VOL|;

see Figure 4

4

-

20

ns

FRFM

differential rise/fall time

matching (tFR/tFF)

excluding the ﬁrst transition

from idle state

90

-

111.1

%

VCRS

output signal crossover

voltage

excluding the ﬁrst transition

from idle state; see Figure 5

[1] 1.3

-

2.0

V

Driver timing

tPLH(drv)

driver propagation delay

(VPO/VO, VMO/FSE0 to

D

+,D−)

LOW-to-HIGH; see Figure 5

--18

ns

tPHL(drv)

driver propagation delay

(VPO/VO, VMO/FSE0 to

D

+,D−)

HIGH-to-LOW; see Figure 5

--18

ns

tPHZ

driver disable delay (OE to

D

+, D−)

HIGH-to-OFF; see Figure 6

--15

ns

tPLZ

driver disable delay

(OE to D

+, D−)

LOW-to-OFF; see Figure 6

--15

ns

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