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NB3M8T3910GMNR2G Datasheet(PDF) 3 Page - ON Semiconductor |
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NB3M8T3910GMNR2G Datasheet(HTML) 3 Page - ON Semiconductor |
3 / 20 page NB3M8T3910G www.onsemi.com 3 Table 1. PIN DESCRIPTION Number Description Default (Internal Resistors) Type Name 15, 42 VDD Power VDD Positive Supply pin for core logic. VDD pins must all be externally connected to a power supply to guarantee proper operation. Bypass with 0.01 mF cap to GND. 16, 17 XTAL_IN, XTAL_OUT Input Crystal input / output. XTAL_IN can also be driven by X0, TCX0 or other external single−ended clock. 19, 22 SEL0 SEL1 Input Pulldown Input clock selectors. See Table 3 for function. LVCMOS/LVTTL interface levels. 20 CLK0 Input Pulldown Non−inverting clock input 0. LVPECL, LVDS, SSTL, HCSL levels. 21 CLK0 Input Pullup / Pulldown Inverting differential clock input 0. LVPECL, LVDS, SSTL, HCSL, LVCMOS levels. Internal bias to VDD B 2. 23, 39 SMODEB0 / SMODEB1 Input Pulldown Output driver selects for BANK B. See Table 6 for function. LVCMOS/LVTTL levels. 25,26 QB4, QB4 Output Bank B differential output pair Q4. Configurable as LVPECL / LVDS / HCSL 27,28 QB3, QB3 Output Bank B differential output pair Q3. Configurable as LVPECL / LVDS / HCSL. 30,31 QB2, QB2 Output Bank B differential output pair Q2. Configurable as LVPECL / LVDS / HCSL. 33,34 QB1, QB1 Output Bank B differential output pair Q1. Configurable as LVPECL / LVDS / HCSL. 35,36 QB0, QB0 Output Bank B differential output pair Q0. Configurable as LVPECL / LVDS / HCSL. 38 IREF Output Connect a fixed 475 W precision resistor from this pin to ground to provide the output reference current. Required for HCSL, not used for LVPECL or LVDS. 40 CLK1 Input Pullup / Pulldown Inverting differential clock input 1. LVPECL, LVDS, SSTL, HCSL levels internal bias to VDD/2. Internal bias to VDD B 2. 41 CLK1 Input Pulldown Non−inverting differential clock input 1. LVPECL, LVDS, SSTL, HCSL, LVCMOS levels. 44 REFOUT Output Reference output, LVCMOS. 46 OE_SE Input Pulldown Synchronous Enable Control for REFOUT. LVCMOS/LVTTL levels. EP EXPOSED PAD Thermal The Exposed Pad (EP) on the QFN−48 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to the die, and must be electrically connected to GND. Table 2. PIN CHARACTERISTICS Symbol Parameter Min Typ Max Unit CIN Input Capacitance 4 pF RPU/RPD Input Pullup/Pulldown Resistor 50 k W |
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