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NB3W1200LMNG Datasheet(PDF) 9 Page - ON Semiconductor

Part # NB3W1200LMNG
Description  Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer for PCle
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NB3W1200LMNG Datasheet(HTML) 9 Page - ON Semiconductor

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NB3N1200K, NB3W1200L
www.onsemi.com
9
NB3N1200K / NB3W1200L Output Relational Timing Parameters
Table 5. ELECTRICAL CHARACTERISTICS − Skew and Differential Jitter Parameters
(VDD = VDDA = VDDR = 3.3 V ±5%, TA = 0 − 70°C)
Group
Description
Min
Typ
Max
Units
CLK_IN, DIF[x:0]
(Notes 9, 10, 12, 13)
Input−to−Output Delay in PLL mode, nominal value
−100
100
ps
CLK_IN, DIF[x:0]
(Notes 10, 11, 13)
Input−to−Output Delay in Bypass mode, nominal value
2.5
4.5
ns
CLK_IN, DIF[x:0]
(Notes 10, 11, 13)
Input−to−Output Delay variation in PLL mode
(over voltage and temperature), nominal value
|100|
ps
CLK_IN, DIF[x:0]
(Notes 10, 11, 13)
Input−to−Output Delay variation in Bypass mode
(over voltage and temperature), nominal value
|250|
ps
DIF[11:0]
(Notes 9, 10, 11, 13)
Output−to−Output Skew across all 12 outputs
(Common to Bypass and PLL mode)
0
50
ps
9. Measured into fixed 2 pF load capacitance
. Input to output skew is measured at the first output edge following the corresponding input.
10. Measured from differential cross−point to differential cross−point.
11. All Bypass Mode Input−to−Output specs refer to the timing between an input edge and the specific output edge created by it.
12. This parameter is deterministic for a given device.
13. Measured with scope averaging on to find mean value.


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