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NB3N1900KMNTWG Datasheet(PDF) 11 Page - ON Semiconductor

Part # NB3N1900KMNTWG
Description  Differential 1:19 HCSL Clock ZDB/Fanout Buffer for PCIe
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NB3N1900KMNTWG Datasheet(HTML) 11 Page - ON Semiconductor

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NB3N1900K
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Table 14. ELECTRICAL CHARACTERISTICS − PHASE JITTER PARAMETERS
(VDD = VDDA = 3.3 V ±5%, TA = −10°C to +70°C), See Test Loads for Loading Conditions.
Symbol
Parameter
Conditions (Notes 31 and 36)
Min
Typ
Max
Unit
tjphPCIeG1
Jitter, Phase
PCIe Gen 1 (Notes 32 and 33)
36
86
ps (p−p)
tjphPCIeG2
PCIe Gen 2 Lo Band
10 kHz < f < 1.5 MHz (Note 32)
3
ps
(rms)
PCIe Gen 2 High Band
1.5 MHz < f < Nyquist (50 MHz)
(Note 32)
3.1
ps
(rms)
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2−4 MHz, CDR = 10 MHz)
(Note 32)
1
ps
(rms)
tjphQPI_SMI
QPI & SMI
(100.00 MHz or 133.33 MHz,
4.8 Gb/s, 6.4 Gb/s 12UI) (Note 34)
0.5
ps
(rms)
QPI & SMI
(100.00 MHz, 8.0 Gb/s, 12UI) (Note 34)
0.3
ps
(rms)
QPI & SMI
(100.00 MHz, 9.6 Gb/s, 12UI) (Note 34)
0.2
ps
(rms)
tjphPCIeG1
Additive Phase Jitter, Bypass
mode
PCIe Gen 1 (Notes 32 and 33)
10
ps (p−p)
tjphPCIeG2
PCIe Gen 2 Lo Band
10 kHz < f < 1.5 MHz (Notes 32 and 35)
0.3
ps
(rms)
PCIe Gen 2 High Band
1.5 MHz < f < Nyquist (50 MHz)
(Notes 32 and 35)
0.7
ps
(rms)
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2−4 MHz, CDR = 10 MHz)
(Notes 32 and 35)
0.3
ps
(rms)
tjphQPI_SMI
QPI & SMI
(100.00 MHz or 133.33 MHz, 4.8 Gb/s,
6.4 Gb/s 12UI) (Notes 34 and 35)
0.3
ps
(rms)
QPI & SMI
(100.00 MHz, 8.0 Gb/s, 12UI) (Notes 34 and 35)
0.1
ps
(rms)
QPI & SMI
(100.00 MHz, 9.6 Gb/s, 12UI) (Notes 34 and 35)
0.1
ps
(rms)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
31. Applies to all outputs.
32. See http://www.pcisig.com for complete specs
33. Sample size of at least 100K cycles. This figures extrapolates to 108 ps pk−pk @ 1M cycles for a BER of 1−12.
34. Calculated from Intel−supplied Clock Jitter Tool v 1.6.3.
35. For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)2 = (total jitter)2
- (input jitter)2
36. Guaranteed by design and characterization, not tested in production


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