NB3V110xC Series

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2

NB3V1102C

NB3V1103C

NB3V1104C

NB3V1106C

Figure 1. Pin Configuration

TSSOP−14

TSSOP−8 and WDFN8

1

2

3

4

8

7

6

5

CLKIN

OE

Q0

GND

Q1

NC/Q3

VDD

NC/Q2

CLKIN

OE

Q0

GND

VDD

Q4

GND

Q1

Q3

VDD

Q2

GND

Q5

VDD

1

2

3

4

5

6

7

14

13

12

11

10

9

8

NB3V1108C

TSSOP−16

CLKIN

OE

Q0

GND

VDD

Q4

GND

Q1

Q3

VDD

Q2

GND

Q5

VDD

1

2

3

4

5

6

7

14

13

12

11

10

9

15

Q6

Q7

8

16

Table 1. PIN DESCRIPTION

Devices

LVCMOS Clock

Input

LVCMOS Clock

Output Enable

LVCMOS Clock Output

Device

Supply Voltage

Device

Ground

CLKIN

OE

Q0, Q1, ... Q7

GND

NB3V1102C

1

2

3, 8

6

4

NB3V1103C

1

2

3, 8, 5

6

4

NB3V1104C

1

2

3, 8, 5, 7

6

4

NB3V1106C

1

2

3, 14, 11, 13, 6, 9

5, 8, 12

4, 7, 10

NB3V1108C

1

2

3, 16, 13, 15, 6, 11, 8, 9

5, 10, 14

4, 7, 12

NOTE: Pins not mentioned in the table are NC.

Table 2. OUTPUT LOGIC TABLE

INPUTS

OUTPUTS

CLKIN

OE

Qn

X

L

L

L

H

L

H

H

H

Over operating free−air temperature range (unless otherwise noted)

Symbol

Condition

Value

Unit

Supply Voltage Range

–0.5 to 4.6

V

Input Voltage Range (Note 2)

V

Output Voltage Range (Note 2)

V

Input Current

±20

mA

Continuous Output Current

±50

mA

q

JA

Thermal Resistance (Junction−to−Ambient)

104

°C/W

Maximum Junction Temperature

125

°C

Storage Temperature Range

–65 to 150

°C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

2. For additional information, see Application Note AND8003/D.