NB4L52

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2

R

Figure 2. Pinout (Top View)

D

D

Q

CLK

Q

1

2

3

4

5

678

9

10

11

12

13

14

15

16

R

CLK

NB4L52

Exposed Pad (EP)

Table 2. PIN DESCRIPTION

Pin

Name

I/O

Description

1

−

Internal 50 W Termination Pin. (See Table 4)

2

D

ECL, CML, LVCMOS,

LVDS, LVTTL Input

Noninverted Differential Input. (Note 1)

3

D

ECL, CML, LVCMOS,

LVDS, LVTTL Input

Inverted Differential Input. (Note 1)

4

−

Internal 50 W Termination Pin. (See Table 4)

5

−

Internal 50 W Termination Pin. (See Table 4)

6

CLK

ECL, CML, LVCMOS,

LVDS, LVTTL Input

Noninverted Differential Input. (Note 1)

7

CLK

ECL, CML, LVCMOS,

LVDS, LVTTL Input

Inverted Differential Input. (Note 1)

8

−

Internal 50 W Termination Pin. (See Table 4)

9

−

Negative Supply Voltage

10

Q

ECL Output

11

Q

ECL Output

12

−

Positive Supply Voltage

13

−

Internal 50 W Termination Pin. (See Table 4)

14

R

LVECL, LVCMOS,

LVTTL Input

Noninverted Differential Reset Input. (Note 1)

15

R

LVECL, LVCMOS,

LVTTL Input

Inverted Differential Reset Input. (Note 1)

16

−

Internal 50 W Termination Pin. (See Table 4)

−

EP

−

The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die

for improved heat transfer out of package. The pad is not electrically connected to the die,

1. In the differential configuration when the input termination pin (VTD, VTD, VTR, VTR, VTCLK, VTCLK) are connected to a common

termination voltage or left open, and if no signal is applied on D/D,CLK/CLK,R/R input then the device will be susceptible to self−oscillation.