NB4L52 datasheet(7/8 Pages) ONSEMI

Part #	NB4L52

Description	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop

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NB4L52

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Figure 10. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices.)

Driver

Device

Receiver

Device

QD

Q

D

Zo = 50 W

50 W

VTT

VTT = VCC − 2.0 V

NB6L239

ORDERING INFORMATION

Device

Package

Shipping†

NB4L52MNG

QFN−16, 3 x 3 mm

(Pb−Free)

123 Units / Rail

NB4L52MNR2G

QFN−16, 3 x 3 mm

(Pb−Free)

3000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

Resource Reference of Application Notes

AN1405/D

− ECL Clock Distribution Techniques

AN1406/D

− Designing with PECL (ECL at +5.0 V)

AN1503/D

− ECLinPS I/O SPiCE Modeling Kit

AN1504/D

− Metastability and the ECLinPS Family

AN1568/D

− Interfacing Between LVDS and ECL

AN1672/D

− The ECL Translator Guide

AND8001/D − Odd Number Counters Design

AND8002/D − Marking and Date Codes

AND8020/D − Termination of ECL Logic Devices

AND8066/D − Interfacing with ECLinPS

AND8090/D − AC Characteristics of ECL Devices

Similar Part No. - NB4L52

Manufacturer	Part #	Datasheet	Description
ON Semiconductor	NB4L52	135Kb / 8P	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVPECL Translator w/ Internal Termination January, 2007 ??Rev. 2
	NB4L52MNG	135Kb / 8P	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVPECL Translator w/ Internal Termination January, 2007 ??Rev. 2
	NB4L52MNR2G	135Kb / 8P	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVPECL Translator w/ Internal Termination January, 2007 ??Rev. 2
	NB4L52	135Kb / 8P	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVPECL Translator w/ Internal Termination January, 2007 ??Rev. 2

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