NB4L6254

http://onsemi.com

3

Table 1. PIN DESCRIPTION

Pin Name

I/O

Description

CLK0, CLK0

LVPECL Input

Differential reference clock signal input 0.

CLK1, CLK1

LVPECL Input

Differential reference clock signal input 1.

OEAb, OEB

LVCMOS Input

Output Enable

SEL0, SEL1

LVCMOS Input

Clock Switch Select

QA[0−2], QA[0−2]

QB[0−2], QB[0−2]

LVPECL Output

Differential LVPECL Clock Outputs, (banks A and B) Typically terminated with 50 W

GND

Power Supply

Negative Supply Voltage

Power Supply

for correct DC and AC operation.

EP

The exposed pad (EP) on the QFN−32 package bottom is thermally connected to the

die for improved heat transfer out of the package. THe exposed pad must be attached

to a heat−sinking conduit. The pad is electrically connected to GND.

Table 2. FUNCTION TABLE

Control

Default

0

1

OEA

0

QA[0−2], QA[0−2] are active. Deassertion of

OEA can be asynchronous to the reference

clock without generation of output runt pulses

QA[0−2] = L, QA[0−2] = H (outputs disabled). Assertion of

OE can be asynchronous to the reference clock without

generation of output runt pulses

OEB

0

QB[0−2], QB[0−2] are active. Deassertion of

OEB can be asynchronous to the reference

clock without generation of output runt pulses

QB[0−2] = L, QB[0−2] = H (outputs disabled). Assertion of

OE can be asynchronous to the reference clock without

generation of output runt pulses

SEL0,

SEL1

00

Refer to Table 3

Refer to Table 3

Table 3. CLOCK SELECT CONTROL

SEL0

SEL1

CLK0 Routed To

CLK1 Routed to

Application Mode

0

0

QA[0:2] and QB[0:2]

−

1:6 Fanout of CLK0

0

1

−

QA[0:2] and QB[0:2]

1:6 Fanout of CLK1

1

0

QA[0:2]

QB[0:2]

Dual 1:3 Buffer

1

1

QB[0:2]

QA[0:2]

Dual 1:3 Buffer (Crossed)