NB6L295

http://onsemi.com

8

Figure 7. Serial Data Interface, Shift Register, Data Latch, Programmable Delay Channels

01

PD1 Latch

PD0 Latch

PD0 Delay

PD1 Delay

SLOAD

Q1/Q1

Q0/Q0

SDATA

SCLK

11−Bit Shift Register

MSEL

Serial Data Interface Loading

Loading the device through the 3 input Serial Data Interface (SDI) is accomplished by sending data into the SDIN pin by

using the SCLK input pin and latching the data with the SLOAD input pin. The 11−bit SHIFT REGISTER shifts once per rising

edge of the SCLK input. The serial input SDIN must meet setup and hold timing as specified in the AC Characteristics section

of this document for each bit and clock pulse. The SLOAD line loads the value of the shift register on a LOW−to−HIGH edge

transition (transparent state) into a data Latch register and latches the data with a subsequent HIGH−to−LOW edge transition.

Further changes in SDIN or SCLK are not recognized by the latched register. The internal multiplexer states are set by the PSEL

and MSEL bits in the SHIFT register. Figure 6 shows the timing diagram of a typical load sequence.

Input EN should be LOW (enabled) prior to SDI programming, then pulled HIGH (disabled) during programming. After

programming, the EN should be returned LOW (enabled) for functional delay operation.

The disabling of EN (HIGH) forces Qx LOW and Qx HIGH and is included during programming to prevent (or mask out)

any potential runt pulses or extended pulses which might occur in the internal delay gates programming switching, but it is not

required for programming.

SDIN

SCLK

SLOAD

LSB

EN

MSB

PSEL MSEL

D0

D1

D2

D3

D4

D5

D6

D7

D8

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

Figure 8. SDI Timing Diagram

SCLK