NB6N239S

http://onsemi.com

2

SELA0

Figure 2. Pinout: QFN−16 (Top View)

CLK

CLK

VT

EN

QA

QB

SELB1

QA

GND

QB

1

2

3

4

5

678

9

10

11

12

13

14

15

16

SELA1

SELB0

NB6N239S

MR

Exposed Pad (EP)

Table 1. PIN DESCRIPTION

Pin

Name

I/O

Description

1

VT

Internal 100 W Center−Tapped Termination Pin for CLK and CLK.

2

CLK

LVDS, LVPECL, CML,

HCSL, HSTL Input

Noninverted Differential CLOCK Input.

3

CLK

LVDS, LVPECL, CML,

HCSL, HSTL Input

Inverted Differential CLOCK Input.

4

Output Voltage Reference for Capacitor Coupled Inputs, only.

5

EN*

LVCMOS/LVTTL Input

Synchronous Output Enable

6

SELB0*

LVCMOS/LVTTL Input

Clock Divide Select Pin

7

SELB1*

LVCMOS/LVTTL Input

Clock Divide Select Pin

8

GND

Power Supply

Negative Supply Voltage

9

QB

LVDS Output

Inverted Differential Output. Typically terminated with 100 W across differential outputs.

10

QB

LVDS Output

Noninverted Differential Output. Typically terminated with 100 W across differential

outputs.

11

QA

LVDS Output

Inverted Differential Output. Typically terminated with 100 W across differential outputs.

12

QA

LVDS Output

Noninverted Differential Output. Typically terminated with 100 W across differential out-

puts.

13

Power Supply

Positive Supply Voltage.

14

SELA1*

LVCMOS/LVTTL Input

Clock Divide Select Pin

15

SELA0*

LVCMOS/LVTTL Input

Clock Divide Select Pin

16

MR**

LVCMOS/LVTTL Input

Master Reset Asynchronous, Default Open High, Asserted LOW

EP

Power Supply (OPT)

The Exposed Pad on the QFN−16 package bottom is thermally connected to the die for

improved heat transfer out of package. The pad is electrically connected to the die, and

is recommended to be electrically and thermally connected to GND on the PC board.

*Pins will default LOW when left OPEN.

**Pins will default HIGH when left OPEN.